[
  {
    "type": "source_project_metadata",
    "source_project_metadata_id": "source_project_metadata_0",
    "software_used_string": "@tscircuit/core@0.0.1830"
  },
  {
    "type": "source_group",
    "source_group_id": "source_group_0",
    "name": "SOC_FANOUT",
    "was_automatically_named": false,
    "parent_source_group_id": "source_group_2"
  },
  {
    "type": "source_group",
    "source_group_id": "source_group_1",
    "name": "DRAM_FANOUT",
    "was_automatically_named": false,
    "parent_source_group_id": "source_group_2"
  },
  {
    "type": "source_group",
    "source_group_id": "source_group_2",
    "name": "AM62L_LPDDR4_RIGHT",
    "is_subcircuit": true,
    "was_automatically_named": false,
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_0",
    "name": "VDD_CORE",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_1",
    "name": "VDDA_1V8",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_2",
    "name": "SOC_DVDD3V3",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": false,
    "is_positive_voltage_source": false,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_3",
    "name": "SOC_DVDD1V8",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": false,
    "is_positive_voltage_source": false,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_4",
    "name": "VDDA_CORE",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net39"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_5",
    "name": "VPP_1V8",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net40"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_6",
    "name": "VDD_MMC1_SD",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net41"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_7",
    "name": "VDDSHV_SD_IO",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net42"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_8",
    "name": "SOC_VDD_RTC",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net43"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_9",
    "name": "SOC_VDDS_RTC_1V8",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net44"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_10",
    "name": "CAP_VDDS_MMC0",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net45"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_11",
    "name": "CAP_VDDS_MMC1",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net46"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_12",
    "name": "CAP_VDDS_MMC2",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net47"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_13",
    "name": "CAP_VDDS_GPMC",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net48"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_14",
    "name": "CAP_VDDS_GENERAL1",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net49"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_15",
    "name": "CAP_VDDSHV_MMC",
    "member_source_group_ids": [],
    "is_ground": false,
    "is_power": true,
    "is_positive_voltage_source": true,
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net50"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_0",
    "name": "A1",
    "pin_number": 1,
    "port_hints": [
      "A1",
      "VSS",
      "pin1",
      "1"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1",
    "name": "A2",
    "pin_number": 2,
    "port_hints": [
      "A2",
      "VSS",
      "pin2",
      "2"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_2",
    "name": "A4",
    "pin_number": 4,
    "port_hints": [
      "A4",
      "VSS",
      "pin4",
      "4"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_3",
    "name": "A10",
    "pin_number": 10,
    "port_hints": [
      "A10",
      "VSS",
      "pin10",
      "10"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_4",
    "name": "A13",
    "pin_number": 13,
    "port_hints": [
      "A13",
      "VSS",
      "pin13",
      "13"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_5",
    "name": "A16",
    "pin_number": 16,
    "port_hints": [
      "A16",
      "VSS",
      "pin16",
      "16"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_6",
    "name": "A19",
    "pin_number": 19,
    "port_hints": [
      "A19",
      "VSS",
      "pin19",
      "19"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_7",
    "name": "A22",
    "pin_number": 22,
    "port_hints": [
      "A22",
      "VSS",
      "pin22",
      "22"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_8",
    "name": "A23",
    "pin_number": 23,
    "port_hints": [
      "A23",
      "VSS",
      "pin23",
      "23"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_9",
    "name": "B1",
    "pin_number": 24,
    "port_hints": [
      "B1",
      "VSS",
      "pin24",
      "24"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_10",
    "name": "B5",
    "pin_number": 28,
    "port_hints": [
      "B5",
      "VSS",
      "pin28",
      "28"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_11",
    "name": "B17",
    "pin_number": 40,
    "port_hints": [
      "B17",
      "VSS",
      "pin40",
      "40"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_12",
    "name": "B20",
    "pin_number": 43,
    "port_hints": [
      "B20",
      "VSS",
      "pin43",
      "43"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_13",
    "name": "B23",
    "pin_number": 46,
    "port_hints": [
      "B23",
      "VSS",
      "pin46",
      "46"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_14",
    "name": "C12",
    "pin_number": 53,
    "port_hints": [
      "C12",
      "VSS",
      "pin53",
      "53"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_15",
    "name": "C18",
    "pin_number": 56,
    "port_hints": [
      "C18",
      "VSS",
      "pin56",
      "56"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_16",
    "name": "D1",
    "pin_number": 60,
    "port_hints": [
      "D1",
      "VSS",
      "pin60",
      "60"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_17",
    "name": "E2",
    "pin_number": 77,
    "port_hints": [
      "E2",
      "VSS",
      "pin77",
      "77"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_18",
    "name": "E6",
    "pin_number": 78,
    "port_hints": [
      "E6",
      "VSS",
      "pin78",
      "78"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_19",
    "name": "E8",
    "pin_number": 79,
    "port_hints": [
      "E8",
      "VSS",
      "pin79",
      "79"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_20",
    "name": "E9",
    "pin_number": 80,
    "port_hints": [
      "E9",
      "VSS",
      "pin80",
      "80"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_21",
    "name": "E10",
    "pin_number": 81,
    "port_hints": [
      "E10",
      "VSS",
      "pin81",
      "81"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_22",
    "name": "E14",
    "pin_number": 85,
    "port_hints": [
      "E14",
      "VSS",
      "pin85",
      "85"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_23",
    "name": "E15",
    "pin_number": 86,
    "port_hints": [
      "E15",
      "VSS",
      "pin86",
      "86"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_24",
    "name": "F5",
    "pin_number": 95,
    "port_hints": [
      "F5",
      "VSS",
      "pin95",
      "95"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_25",
    "name": "F6",
    "pin_number": 96,
    "port_hints": [
      "F6",
      "VSS",
      "pin96",
      "96"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_26",
    "name": "F18",
    "pin_number": 97,
    "port_hints": [
      "F18",
      "VSS",
      "pin97",
      "97"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_27",
    "name": "G7",
    "pin_number": 106,
    "port_hints": [
      "G7",
      "VSS",
      "pin106",
      "106"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_28",
    "name": "G8",
    "pin_number": 107,
    "port_hints": [
      "G8",
      "VSS",
      "pin107",
      "107"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_29",
    "name": "G9",
    "pin_number": 108,
    "port_hints": [
      "G9",
      "VSS",
      "pin108",
      "108"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_30",
    "name": "G12",
    "pin_number": 111,
    "port_hints": [
      "G12",
      "VSS",
      "pin111",
      "111"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_31",
    "name": "G15",
    "pin_number": 114,
    "port_hints": [
      "G15",
      "VSS",
      "pin114",
      "114"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_32",
    "name": "G16",
    "pin_number": 115,
    "port_hints": [
      "G16",
      "VSS",
      "pin115",
      "115"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_33",
    "name": "G17",
    "pin_number": 116,
    "port_hints": [
      "G17",
      "VSS",
      "pin116",
      "116"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_34",
    "name": "H1",
    "pin_number": 120,
    "port_hints": [
      "H1",
      "VSS",
      "pin120",
      "120"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_35",
    "name": "H7",
    "pin_number": 126,
    "port_hints": [
      "H7",
      "VSS",
      "pin126",
      "126"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_36",
    "name": "H14",
    "pin_number": 130,
    "port_hints": [
      "H14",
      "VSS",
      "pin130",
      "130"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_37",
    "name": "H17",
    "pin_number": 132,
    "port_hints": [
      "H17",
      "VSS",
      "pin132",
      "132"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_38",
    "name": "K8",
    "pin_number": 151,
    "port_hints": [
      "K8",
      "VSS",
      "pin151",
      "151"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_39",
    "name": "K9",
    "pin_number": 152,
    "port_hints": [
      "K9",
      "VSS",
      "pin152",
      "152"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_40",
    "name": "K15",
    "pin_number": 156,
    "port_hints": [
      "K15",
      "VSS",
      "pin156",
      "156"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_41",
    "name": "L7",
    "pin_number": 166,
    "port_hints": [
      "L7",
      "VSS",
      "pin166",
      "166"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_42",
    "name": "L9",
    "pin_number": 168,
    "port_hints": [
      "L9",
      "VSS",
      "pin168",
      "168"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_43",
    "name": "L13",
    "pin_number": 170,
    "port_hints": [
      "L13",
      "VSS",
      "pin170",
      "170"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_44",
    "name": "L16",
    "pin_number": 172,
    "port_hints": [
      "L16",
      "VSS",
      "pin172",
      "172"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_45",
    "name": "L18",
    "pin_number": 174,
    "port_hints": [
      "L18",
      "VSS",
      "pin174",
      "174"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_46",
    "name": "M1",
    "pin_number": 180,
    "port_hints": [
      "M1",
      "VSS",
      "pin180",
      "180"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_47",
    "name": "M12",
    "pin_number": 187,
    "port_hints": [
      "M12",
      "VSS",
      "pin187",
      "187"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_48",
    "name": "N7",
    "pin_number": 201,
    "port_hints": [
      "N7",
      "VSS",
      "pin201",
      "201"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_49",
    "name": "N9",
    "pin_number": 203,
    "port_hints": [
      "N9",
      "VSS",
      "pin203",
      "203"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_50",
    "name": "N11",
    "pin_number": 204,
    "port_hints": [
      "N11",
      "VSS",
      "pin204",
      "204"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_51",
    "name": "N13",
    "pin_number": 205,
    "port_hints": [
      "N13",
      "VSS",
      "pin205",
      "205"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_52",
    "name": "N16",
    "pin_number": 207,
    "port_hints": [
      "N16",
      "VSS",
      "pin207",
      "207"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_53",
    "name": "P9",
    "pin_number": 218,
    "port_hints": [
      "P9",
      "VSS",
      "pin218",
      "218"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_54",
    "name": "P15",
    "pin_number": 222,
    "port_hints": [
      "P15",
      "VSS",
      "pin222",
      "222"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_55",
    "name": "R1",
    "pin_number": 226,
    "port_hints": [
      "R1",
      "VSS",
      "pin226",
      "226"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_56",
    "name": "R8",
    "pin_number": 228,
    "port_hints": [
      "R8",
      "VSS",
      "pin228",
      "228"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_57",
    "name": "R13",
    "pin_number": 231,
    "port_hints": [
      "R13",
      "VSS",
      "pin231",
      "231"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_58",
    "name": "R15",
    "pin_number": 232,
    "port_hints": [
      "R15",
      "VSS",
      "pin232",
      "232"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_59",
    "name": "T2",
    "pin_number": 237,
    "port_hints": [
      "T2",
      "VSS",
      "pin237",
      "237"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_60",
    "name": "T7",
    "pin_number": 242,
    "port_hints": [
      "T7",
      "VSS",
      "pin242",
      "242"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_61",
    "name": "T8",
    "pin_number": 243,
    "port_hints": [
      "T8",
      "VSS",
      "pin243",
      "243"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_62",
    "name": "T19",
    "pin_number": 250,
    "port_hints": [
      "T19",
      "VSS",
      "pin250",
      "250"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_63",
    "name": "U7",
    "pin_number": 258,
    "port_hints": [
      "U7",
      "VSS",
      "pin258",
      "258"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_64",
    "name": "U8",
    "pin_number": 259,
    "port_hints": [
      "U8",
      "VSS",
      "pin259",
      "259"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_65",
    "name": "U10",
    "pin_number": 261,
    "port_hints": [
      "U10",
      "VSS",
      "pin261",
      "261"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_66",
    "name": "U13",
    "pin_number": 264,
    "port_hints": [
      "U13",
      "VSS",
      "pin264",
      "264"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_67",
    "name": "U14",
    "pin_number": 265,
    "port_hints": [
      "U14",
      "VSS",
      "pin265",
      "265"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_68",
    "name": "U15",
    "pin_number": 266,
    "port_hints": [
      "U15",
      "VSS",
      "pin266",
      "266"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_69",
    "name": "U17",
    "pin_number": 268,
    "port_hints": [
      "U17",
      "VSS",
      "pin268",
      "268"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_70",
    "name": "U20",
    "pin_number": 269,
    "port_hints": [
      "U20",
      "VSS",
      "pin269",
      "269"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_71",
    "name": "V3",
    "pin_number": 274,
    "port_hints": [
      "V3",
      "VSS",
      "pin274",
      "274"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_72",
    "name": "V18",
    "pin_number": 278,
    "port_hints": [
      "V18",
      "VSS",
      "pin278",
      "278"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_73",
    "name": "V19",
    "pin_number": 279,
    "port_hints": [
      "V19",
      "VSS",
      "pin279",
      "279"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_74",
    "name": "W9",
    "pin_number": 288,
    "port_hints": [
      "W9",
      "VSS",
      "pin288",
      "288"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_75",
    "name": "W10",
    "pin_number": 289,
    "port_hints": [
      "W10",
      "VSS",
      "pin289",
      "289"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_76",
    "name": "W12",
    "pin_number": 291,
    "port_hints": [
      "W12",
      "VSS",
      "pin291",
      "291"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_77",
    "name": "W14",
    "pin_number": 293,
    "port_hints": [
      "W14",
      "VSS",
      "pin293",
      "293"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_78",
    "name": "W15",
    "pin_number": 294,
    "port_hints": [
      "W15",
      "VSS",
      "pin294",
      "294"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_79",
    "name": "W16",
    "pin_number": 295,
    "port_hints": [
      "W16",
      "VSS",
      "pin295",
      "295"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_80",
    "name": "W18",
    "pin_number": 296,
    "port_hints": [
      "W18",
      "VSS",
      "pin296",
      "296"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_81",
    "name": "Y1",
    "pin_number": 299,
    "port_hints": [
      "Y1",
      "VSS",
      "pin299",
      "299"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_82",
    "name": "Y20",
    "pin_number": 311,
    "port_hints": [
      "Y20",
      "VSS",
      "pin311",
      "311"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_83",
    "name": "Y21",
    "pin_number": 312,
    "port_hints": [
      "Y21",
      "VSS",
      "pin312",
      "312"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_84",
    "name": "AA4",
    "pin_number": 317,
    "port_hints": [
      "AA4",
      "VSS",
      "pin317",
      "317"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_85",
    "name": "AA20",
    "pin_number": 325,
    "port_hints": [
      "AA20",
      "VSS",
      "pin325",
      "325"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_86",
    "name": "AB1",
    "pin_number": 328,
    "port_hints": [
      "AB1",
      "VSS",
      "pin328",
      "328"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_87",
    "name": "AB7",
    "pin_number": 334,
    "port_hints": [
      "AB7",
      "VSS",
      "pin334",
      "334"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_88",
    "name": "AB21",
    "pin_number": 348,
    "port_hints": [
      "AB21",
      "VSS",
      "pin348",
      "348"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_89",
    "name": "AB23",
    "pin_number": 350,
    "port_hints": [
      "AB23",
      "VSS",
      "pin350",
      "350"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_90",
    "name": "AC1",
    "pin_number": 351,
    "port_hints": [
      "AC1",
      "VSS",
      "pin351",
      "351"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_91",
    "name": "AC2",
    "pin_number": 352,
    "port_hints": [
      "AC2",
      "VSS",
      "pin352",
      "352"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_92",
    "name": "AC11",
    "pin_number": 361,
    "port_hints": [
      "AC11",
      "VSS",
      "pin361",
      "361"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_93",
    "name": "AC14",
    "pin_number": 364,
    "port_hints": [
      "AC14",
      "VSS",
      "pin364",
      "364"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_94",
    "name": "AC19",
    "pin_number": 369,
    "port_hints": [
      "AC19",
      "VSS",
      "pin369",
      "369"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_95",
    "name": "AC22",
    "pin_number": 372,
    "port_hints": [
      "AC22",
      "VSS",
      "pin372",
      "372"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_96",
    "name": "AC23",
    "pin_number": 373,
    "port_hints": [
      "AC23",
      "VSS",
      "pin373",
      "373"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_97",
    "name": "J9",
    "pin_number": 142,
    "port_hints": [
      "J9",
      "VDD_CORE",
      "pin142",
      "142"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_98",
    "name": "J11",
    "pin_number": 143,
    "port_hints": [
      "J11",
      "VDD_CORE",
      "pin143",
      "143"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_99",
    "name": "J13",
    "pin_number": 144,
    "port_hints": [
      "J13",
      "VDD_CORE",
      "pin144",
      "144"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_100",
    "name": "J15",
    "pin_number": 145,
    "port_hints": [
      "J15",
      "VDD_CORE",
      "pin145",
      "145"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_101",
    "name": "K10",
    "pin_number": 153,
    "port_hints": [
      "K10",
      "VDD_CORE",
      "pin153",
      "153"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_102",
    "name": "K14",
    "pin_number": 155,
    "port_hints": [
      "K14",
      "VDD_CORE",
      "pin155",
      "155"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_103",
    "name": "L15",
    "pin_number": 171,
    "port_hints": [
      "L15",
      "VDD_CORE",
      "pin171",
      "171"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_104",
    "name": "M14",
    "pin_number": 188,
    "port_hints": [
      "M14",
      "VDD_CORE",
      "pin188",
      "188"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_105",
    "name": "N15",
    "pin_number": 206,
    "port_hints": [
      "N15",
      "VDD_CORE",
      "pin206",
      "206"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_106",
    "name": "P10",
    "pin_number": 219,
    "port_hints": [
      "P10",
      "VDD_CORE",
      "pin219",
      "219"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_107",
    "name": "P12",
    "pin_number": 220,
    "port_hints": [
      "P12",
      "VDD_CORE",
      "pin220",
      "220"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_108",
    "name": "P14",
    "pin_number": 221,
    "port_hints": [
      "P14",
      "VDD_CORE",
      "pin221",
      "221"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_109",
    "name": "R9",
    "pin_number": 229,
    "port_hints": [
      "R9",
      "VDD_CORE",
      "pin229",
      "229"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "0.1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_110",
    "name": "R11",
    "pin_number": 230,
    "port_hints": [
      "R11",
      "VDD_CORE",
      "pin230",
      "230"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "0.1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_111",
    "name": "M10",
    "pin_number": 186,
    "port_hints": [
      "M10",
      "VDDA_DDR_PLL0",
      "pin186",
      "186"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "0.1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_112",
    "name": "L8",
    "pin_number": 167,
    "port_hints": [
      "L8",
      "VDDS_DDR",
      "pin167",
      "167"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_113",
    "name": "M7",
    "pin_number": 184,
    "port_hints": [
      "M7",
      "VDDS_DDR",
      "pin184",
      "184"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_114",
    "name": "M8",
    "pin_number": 185,
    "port_hints": [
      "M8",
      "VDDS_DDR",
      "pin185",
      "185"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_115",
    "name": "N8",
    "pin_number": 202,
    "port_hints": [
      "N8",
      "VDDS_DDR",
      "pin202",
      "202"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_116",
    "name": "P8",
    "pin_number": 217,
    "port_hints": [
      "P8",
      "VDDS_DDR",
      "pin217",
      "217"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_117",
    "name": "G14",
    "pin_number": 113,
    "port_hints": [
      "G14",
      "VDDA_1P8_DSI",
      "pin113",
      "113"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "0.1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_118",
    "name": "T12",
    "pin_number": 245,
    "port_hints": [
      "T12",
      "VDDA_1P8_USB",
      "pin245",
      "245"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_119",
    "name": "R16",
    "pin_number": 233,
    "port_hints": [
      "R16",
      "VDDS_OSC0",
      "pin233",
      "233"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_120",
    "name": "N17",
    "pin_number": 208,
    "port_hints": [
      "N17",
      "VDDA_ADC",
      "pin208",
      "208"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_121",
    "name": "L11",
    "pin_number": 169,
    "port_hints": [
      "L11",
      "VDDA_PLL0",
      "pin169",
      "169"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_122",
    "name": "K12",
    "pin_number": 154,
    "port_hints": [
      "K12",
      "VDDA_PLL1",
      "pin154",
      "154"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_123",
    "name": "U12",
    "pin_number": 263,
    "port_hints": [
      "U12",
      "VDDA_3P3_USB",
      "pin263",
      "263"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_124",
    "name": "J16",
    "pin_number": 146,
    "port_hints": [
      "J16",
      "VDDSHV0",
      "pin146",
      "146"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_125",
    "name": "L17",
    "pin_number": 173,
    "port_hints": [
      "L17",
      "VDDSHV0",
      "pin173",
      "173"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_126",
    "name": "G10",
    "pin_number": 109,
    "port_hints": [
      "G10",
      "VDDSHV1",
      "pin109",
      "109"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_127",
    "name": "H10",
    "pin_number": 128,
    "port_hints": [
      "H10",
      "VDDSHV1",
      "pin128",
      "128"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_128",
    "name": "H8",
    "pin_number": 127,
    "port_hints": [
      "H8",
      "VDDSHV2",
      "pin127",
      "127"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_129",
    "name": "M17",
    "pin_number": 190,
    "port_hints": [
      "M17",
      "VDDSHV4",
      "pin190",
      "190"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_130",
    "name": "T14",
    "pin_number": 246,
    "port_hints": [
      "T14",
      "VDDS0",
      "pin246",
      "246"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_131",
    "name": "H16",
    "pin_number": 131,
    "port_hints": [
      "H16",
      "VDDS1",
      "pin131",
      "131"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_132",
    "name": "P16",
    "pin_number": 223,
    "port_hints": [
      "P16",
      "VDDS_WKUP",
      "pin223",
      "223"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_133",
    "name": "U11",
    "pin_number": 262,
    "port_hints": [
      "U11",
      "VDDA_CORE_USB",
      "pin262",
      "262"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "0.1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net39"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_134",
    "name": "H12",
    "pin_number": 129,
    "port_hints": [
      "H12",
      "VDDA_CORE_DSI_CLK",
      "pin129",
      "129"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "0.1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net39"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_135",
    "name": "G13",
    "pin_number": 112,
    "port_hints": [
      "G13",
      "VDDA_CORE_DSI",
      "pin112",
      "112"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "0.1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net39"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_136",
    "name": "N18",
    "pin_number": 209,
    "port_hints": [
      "N18",
      "VPP",
      "pin209",
      "209"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net40"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_137",
    "name": "U16",
    "pin_number": 267,
    "port_hints": [
      "U16",
      "VDDA_3P3_SDIO",
      "pin267",
      "267"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "0.1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net41"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_138",
    "name": "T10",
    "pin_number": 244,
    "port_hints": [
      "T10",
      "VDDSHV3",
      "pin244",
      "244"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "0.1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net42"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_139",
    "name": "T17",
    "pin_number": 248,
    "port_hints": [
      "T17",
      "VDD_RTC",
      "pin248",
      "248"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net43"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_140",
    "name": "T18",
    "pin_number": 249,
    "port_hints": [
      "T18",
      "VDDS_RTC",
      "pin249",
      "249"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": true,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net44"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_141",
    "name": "J8",
    "pin_number": 141,
    "port_hints": [
      "J8",
      "CAP_VDDS_MMC0",
      "pin141",
      "141"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": false,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net45"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_142",
    "name": "U9",
    "pin_number": 260,
    "port_hints": [
      "U9",
      "CAP_VDDS_MMC1",
      "pin260",
      "260"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": false,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net46"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_143",
    "name": "M16",
    "pin_number": 189,
    "port_hints": [
      "M16",
      "CAP_VDDS_MMC2",
      "pin189",
      "189"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": false,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net47"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_144",
    "name": "K16",
    "pin_number": 157,
    "port_hints": [
      "K16",
      "CAP_VDDS_GPMC",
      "pin157",
      "157"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": false,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net48"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_145",
    "name": "G11",
    "pin_number": 110,
    "port_hints": [
      "G11",
      "CAP_VDDS_GENERAL1",
      "pin110",
      "110"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": false,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "1uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net49"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_146",
    "name": "T16",
    "pin_number": 247,
    "port_hints": [
      "T16",
      "CAP_VDDSHV_MMC",
      "pin247",
      "247"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "requires_power": false,
    "should_have_decoupling_capacitor": true,
    "recommended_decoupling_capacitor_capacitance": "3.3uF",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net50"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_147",
    "name": "L5",
    "pin_number": 164,
    "port_hints": [
      "L5",
      "DDR0_A0",
      "pin164",
      "164"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net19"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_148",
    "name": "H6",
    "pin_number": 125,
    "port_hints": [
      "H6",
      "DDR0_A1",
      "pin125",
      "125"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net20"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_149",
    "name": "L6",
    "pin_number": 165,
    "port_hints": [
      "L6",
      "DDR0_A2",
      "pin165",
      "165"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net21"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_150",
    "name": "K2",
    "pin_number": 150,
    "port_hints": [
      "K2",
      "DDR0_A3",
      "pin150",
      "150"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net22"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_151",
    "name": "J1",
    "pin_number": 139,
    "port_hints": [
      "J1",
      "DDR0_A4",
      "pin139",
      "139"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net23"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_152",
    "name": "H5",
    "pin_number": 124,
    "port_hints": [
      "H5",
      "DDR0_A5",
      "pin124",
      "124"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net24"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_153",
    "name": "L3",
    "pin_number": 162,
    "port_hints": [
      "L3",
      "DDR0_CS0_n",
      "pin162",
      "162"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net25"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_154",
    "name": "K1",
    "pin_number": 149,
    "port_hints": [
      "K1",
      "DDR0_CKE0",
      "pin149",
      "149"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net26"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_155",
    "name": "P1",
    "pin_number": 215,
    "port_hints": [
      "P1",
      "DDR0_CK0",
      "pin215",
      "215"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net27"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_156",
    "name": "P2",
    "pin_number": 216,
    "port_hints": [
      "P2",
      "DDR0_CK0_n",
      "pin216",
      "216"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net28"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_157",
    "name": "G1",
    "pin_number": 103,
    "port_hints": [
      "G1",
      "DDR0_DQS0",
      "pin103",
      "103"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net29"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_158",
    "name": "G2",
    "pin_number": 104,
    "port_hints": [
      "G2",
      "DDR0_DQS0_n",
      "pin104",
      "104"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net30"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_159",
    "name": "V1",
    "pin_number": 272,
    "port_hints": [
      "V1",
      "DDR0_DQS1",
      "pin272",
      "272"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net31"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_160",
    "name": "V2",
    "pin_number": 273,
    "port_hints": [
      "V2",
      "DDR0_DQS1_n",
      "pin273",
      "273"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net32"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_161",
    "name": "J2",
    "pin_number": 140,
    "port_hints": [
      "J2",
      "DDR0_RESET0_n",
      "pin140",
      "140"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net33"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_162",
    "name": "F2",
    "pin_number": 92,
    "port_hints": [
      "F2",
      "DDR0_DM0",
      "pin92",
      "92"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net34"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_163",
    "name": "W2",
    "pin_number": 285,
    "port_hints": [
      "W2",
      "DDR0_DM1",
      "pin285",
      "285"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net35"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_164",
    "name": "E1",
    "pin_number": 76,
    "port_hints": [
      "E1",
      "DDR0_DQ3",
      "pin76",
      "76"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net6"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_165",
    "name": "F1",
    "pin_number": 91,
    "port_hints": [
      "F1",
      "DDR0_DQ2",
      "pin91",
      "91"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net5"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_166",
    "name": "F3",
    "pin_number": 93,
    "port_hints": [
      "F3",
      "DDR0_DQ1",
      "pin93",
      "93"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_167",
    "name": "F4",
    "pin_number": 94,
    "port_hints": [
      "F4",
      "DDR0_DQ0",
      "pin94",
      "94"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net3"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_168",
    "name": "G4",
    "pin_number": 105,
    "port_hints": [
      "G4",
      "DDR0_DQ4",
      "pin105",
      "105"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net7"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_169",
    "name": "H2",
    "pin_number": 121,
    "port_hints": [
      "H2",
      "DDR0_DQ6",
      "pin121",
      "121"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net9"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_170",
    "name": "H3",
    "pin_number": 122,
    "port_hints": [
      "H3",
      "DDR0_DQ7",
      "pin122",
      "122"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net10"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_171",
    "name": "H4",
    "pin_number": 123,
    "port_hints": [
      "H4",
      "DDR0_DQ5",
      "pin123",
      "123"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net8"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_172",
    "name": "T1",
    "pin_number": 236,
    "port_hints": [
      "T1",
      "DDR0_DQ10",
      "pin236",
      "236"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net13"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_173",
    "name": "T3",
    "pin_number": 238,
    "port_hints": [
      "T3",
      "DDR0_DQ9",
      "pin238",
      "238"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net12"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_174",
    "name": "U1",
    "pin_number": 255,
    "port_hints": [
      "U1",
      "DDR0_DQ11",
      "pin255",
      "255"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net14"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_175",
    "name": "U2",
    "pin_number": 256,
    "port_hints": [
      "U2",
      "DDR0_DQ14",
      "pin256",
      "256"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net17"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_176",
    "name": "U4",
    "pin_number": 257,
    "port_hints": [
      "U4",
      "DDR0_DQ12",
      "pin257",
      "257"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net15"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_177",
    "name": "V4",
    "pin_number": 275,
    "port_hints": [
      "V4",
      "DDR0_DQ8",
      "pin275",
      "275"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net11"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_178",
    "name": "V5",
    "pin_number": 276,
    "port_hints": [
      "V5",
      "DDR0_DQ13",
      "pin276",
      "276"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_179",
    "name": "W1",
    "pin_number": 284,
    "port_hints": [
      "W1",
      "DDR0_DQ15",
      "pin284",
      "284"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net18"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_180",
    "name": "pin3",
    "pin_number": 3,
    "port_hints": [
      "pin3",
      "A3",
      "3"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_181",
    "name": "pin5",
    "pin_number": 5,
    "port_hints": [
      "pin5",
      "A5",
      "5"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_182",
    "name": "pin6",
    "pin_number": 6,
    "port_hints": [
      "pin6",
      "A6",
      "6"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_183",
    "name": "pin7",
    "pin_number": 7,
    "port_hints": [
      "pin7",
      "A7",
      "7"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_184",
    "name": "pin8",
    "pin_number": 8,
    "port_hints": [
      "pin8",
      "A8",
      "8"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_185",
    "name": "pin9",
    "pin_number": 9,
    "port_hints": [
      "pin9",
      "A9",
      "9"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_186",
    "name": "pin11",
    "pin_number": 11,
    "port_hints": [
      "pin11",
      "A11",
      "11"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_187",
    "name": "pin12",
    "pin_number": 12,
    "port_hints": [
      "pin12",
      "A12",
      "12"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_188",
    "name": "pin14",
    "pin_number": 14,
    "port_hints": [
      "pin14",
      "A14",
      "14"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_189",
    "name": "pin15",
    "pin_number": 15,
    "port_hints": [
      "pin15",
      "A15",
      "15"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_190",
    "name": "pin17",
    "pin_number": 17,
    "port_hints": [
      "pin17",
      "A17",
      "17"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_191",
    "name": "pin18",
    "pin_number": 18,
    "port_hints": [
      "pin18",
      "A18",
      "18"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_192",
    "name": "pin20",
    "pin_number": 20,
    "port_hints": [
      "pin20",
      "A20",
      "20"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_193",
    "name": "pin21",
    "pin_number": 21,
    "port_hints": [
      "pin21",
      "A21",
      "21"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_194",
    "name": "pin25",
    "pin_number": 25,
    "port_hints": [
      "pin25",
      "B2",
      "25"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_195",
    "name": "pin26",
    "pin_number": 26,
    "port_hints": [
      "pin26",
      "B3",
      "26"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_196",
    "name": "pin27",
    "pin_number": 27,
    "port_hints": [
      "pin27",
      "B4",
      "27"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_197",
    "name": "pin29",
    "pin_number": 29,
    "port_hints": [
      "pin29",
      "B6",
      "29"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_198",
    "name": "pin30",
    "pin_number": 30,
    "port_hints": [
      "pin30",
      "B7",
      "30"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_199",
    "name": "pin31",
    "pin_number": 31,
    "port_hints": [
      "pin31",
      "B8",
      "31"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_200",
    "name": "pin32",
    "pin_number": 32,
    "port_hints": [
      "pin32",
      "B9",
      "32"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_201",
    "name": "pin33",
    "pin_number": 33,
    "port_hints": [
      "pin33",
      "B10",
      "33"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_202",
    "name": "pin34",
    "pin_number": 34,
    "port_hints": [
      "pin34",
      "B11",
      "34"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_203",
    "name": "pin35",
    "pin_number": 35,
    "port_hints": [
      "pin35",
      "B12",
      "35"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_204",
    "name": "pin36",
    "pin_number": 36,
    "port_hints": [
      "pin36",
      "B13",
      "36"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_205",
    "name": "pin37",
    "pin_number": 37,
    "port_hints": [
      "pin37",
      "B14",
      "37"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_206",
    "name": "pin38",
    "pin_number": 38,
    "port_hints": [
      "pin38",
      "B15",
      "38"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_207",
    "name": "pin39",
    "pin_number": 39,
    "port_hints": [
      "pin39",
      "B16",
      "39"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_208",
    "name": "pin41",
    "pin_number": 41,
    "port_hints": [
      "pin41",
      "B18",
      "41"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_209",
    "name": "pin42",
    "pin_number": 42,
    "port_hints": [
      "pin42",
      "B19",
      "42"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_210",
    "name": "pin44",
    "pin_number": 44,
    "port_hints": [
      "pin44",
      "B21",
      "44"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_211",
    "name": "pin45",
    "pin_number": 45,
    "port_hints": [
      "pin45",
      "B22",
      "45"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_212",
    "name": "pin47",
    "pin_number": 47,
    "port_hints": [
      "pin47",
      "C1",
      "47"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_213",
    "name": "pin48",
    "pin_number": 48,
    "port_hints": [
      "pin48",
      "C2",
      "48"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_214",
    "name": "pin49",
    "pin_number": 49,
    "port_hints": [
      "pin49",
      "C4",
      "49"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_215",
    "name": "pin50",
    "pin_number": 50,
    "port_hints": [
      "pin50",
      "C6",
      "50"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_216",
    "name": "pin51",
    "pin_number": 51,
    "port_hints": [
      "pin51",
      "C8",
      "51"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_217",
    "name": "pin52",
    "pin_number": 52,
    "port_hints": [
      "pin52",
      "C11",
      "52"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_218",
    "name": "pin54",
    "pin_number": 54,
    "port_hints": [
      "pin54",
      "C13",
      "54"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_219",
    "name": "pin55",
    "pin_number": 55,
    "port_hints": [
      "pin55",
      "C16",
      "55"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_220",
    "name": "pin57",
    "pin_number": 57,
    "port_hints": [
      "pin57",
      "C20",
      "57"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_221",
    "name": "pin58",
    "pin_number": 58,
    "port_hints": [
      "pin58",
      "C22",
      "58"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_222",
    "name": "pin59",
    "pin_number": 59,
    "port_hints": [
      "pin59",
      "C23",
      "59"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_223",
    "name": "pin61",
    "pin_number": 61,
    "port_hints": [
      "pin61",
      "D2",
      "61"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_224",
    "name": "pin62",
    "pin_number": 62,
    "port_hints": [
      "pin62",
      "D3",
      "62"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_225",
    "name": "pin63",
    "pin_number": 63,
    "port_hints": [
      "pin63",
      "D4",
      "63"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_226",
    "name": "pin64",
    "pin_number": 64,
    "port_hints": [
      "pin64",
      "D6",
      "64"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_227",
    "name": "pin65",
    "pin_number": 65,
    "port_hints": [
      "pin65",
      "D7",
      "65"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_228",
    "name": "pin66",
    "pin_number": 66,
    "port_hints": [
      "pin66",
      "D8",
      "66"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_229",
    "name": "pin67",
    "pin_number": 67,
    "port_hints": [
      "pin67",
      "D11",
      "67"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_230",
    "name": "pin68",
    "pin_number": 68,
    "port_hints": [
      "pin68",
      "D13",
      "68"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_231",
    "name": "pin69",
    "pin_number": 69,
    "port_hints": [
      "pin69",
      "D16",
      "69"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_232",
    "name": "pin70",
    "pin_number": 70,
    "port_hints": [
      "pin70",
      "D17",
      "70"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_233",
    "name": "pin71",
    "pin_number": 71,
    "port_hints": [
      "pin71",
      "D18",
      "71"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_234",
    "name": "pin72",
    "pin_number": 72,
    "port_hints": [
      "pin72",
      "D20",
      "72"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_235",
    "name": "pin73",
    "pin_number": 73,
    "port_hints": [
      "pin73",
      "D21",
      "73"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_236",
    "name": "pin74",
    "pin_number": 74,
    "port_hints": [
      "pin74",
      "D22",
      "74"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_237",
    "name": "pin75",
    "pin_number": 75,
    "port_hints": [
      "pin75",
      "D23",
      "75"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_238",
    "name": "pin82",
    "pin_number": 82,
    "port_hints": [
      "pin82",
      "E11",
      "82"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_239",
    "name": "pin83",
    "pin_number": 83,
    "port_hints": [
      "pin83",
      "E12",
      "83"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_240",
    "name": "pin84",
    "pin_number": 84,
    "port_hints": [
      "pin84",
      "E13",
      "84"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_241",
    "name": "pin87",
    "pin_number": 87,
    "port_hints": [
      "pin87",
      "E16",
      "87"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_242",
    "name": "pin88",
    "pin_number": 88,
    "port_hints": [
      "pin88",
      "E18",
      "88"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_243",
    "name": "pin89",
    "pin_number": 89,
    "port_hints": [
      "pin89",
      "E22",
      "89"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_244",
    "name": "pin90",
    "pin_number": 90,
    "port_hints": [
      "pin90",
      "E23",
      "90"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_245",
    "name": "pin98",
    "pin_number": 98,
    "port_hints": [
      "pin98",
      "F19",
      "98"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_246",
    "name": "pin99",
    "pin_number": 99,
    "port_hints": [
      "pin99",
      "F20",
      "99"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_247",
    "name": "pin100",
    "pin_number": 100,
    "port_hints": [
      "pin100",
      "F21",
      "100"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_248",
    "name": "pin101",
    "pin_number": 101,
    "port_hints": [
      "pin101",
      "F22",
      "101"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_249",
    "name": "pin102",
    "pin_number": 102,
    "port_hints": [
      "pin102",
      "F23",
      "102"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_250",
    "name": "pin117",
    "pin_number": 117,
    "port_hints": [
      "pin117",
      "G20",
      "117"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_251",
    "name": "pin118",
    "pin_number": 118,
    "port_hints": [
      "pin118",
      "G22",
      "118"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_252",
    "name": "pin119",
    "pin_number": 119,
    "port_hints": [
      "pin119",
      "G23",
      "119"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_253",
    "name": "pin133",
    "pin_number": 133,
    "port_hints": [
      "pin133",
      "H18",
      "133"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_254",
    "name": "pin134",
    "pin_number": 134,
    "port_hints": [
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      "H19",
      "134"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_255",
    "name": "pin135",
    "pin_number": 135,
    "port_hints": [
      "pin135",
      "H20",
      "135"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_256",
    "name": "pin136",
    "pin_number": 136,
    "port_hints": [
      "pin136",
      "H21",
      "136"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_257",
    "name": "pin137",
    "pin_number": 137,
    "port_hints": [
      "pin137",
      "H22",
      "137"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_258",
    "name": "pin138",
    "pin_number": 138,
    "port_hints": [
      "pin138",
      "H23",
      "138"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_259",
    "name": "pin147",
    "pin_number": 147,
    "port_hints": [
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      "J22",
      "147"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_260",
    "name": "pin148",
    "pin_number": 148,
    "port_hints": [
      "pin148",
      "J23",
      "148"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_261",
    "name": "pin158",
    "pin_number": 158,
    "port_hints": [
      "pin158",
      "K22",
      "158"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_262",
    "name": "pin159",
    "pin_number": 159,
    "port_hints": [
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      "K23",
      "159"
    ],
    "source_component_id": "source_component_0",
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  {
    "type": "source_port",
    "source_port_id": "source_port_263",
    "name": "pin160",
    "pin_number": 160,
    "port_hints": [
      "pin160",
      "L1",
      "160"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_264",
    "name": "pin161",
    "pin_number": 161,
    "port_hints": [
      "pin161",
      "L2",
      "161"
    ],
    "source_component_id": "source_component_0",
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  {
    "type": "source_port",
    "source_port_id": "source_port_265",
    "name": "pin163",
    "pin_number": 163,
    "port_hints": [
      "pin163",
      "L4",
      "163"
    ],
    "source_component_id": "source_component_0",
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  {
    "type": "source_port",
    "source_port_id": "source_port_266",
    "name": "pin175",
    "pin_number": 175,
    "port_hints": [
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      "L19",
      "175"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_267",
    "name": "pin176",
    "pin_number": 176,
    "port_hints": [
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      "L20",
      "176"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_268",
    "name": "pin177",
    "pin_number": 177,
    "port_hints": [
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      "L21",
      "177"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_269",
    "name": "pin178",
    "pin_number": 178,
    "port_hints": [
      "pin178",
      "L22",
      "178"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_270",
    "name": "pin179",
    "pin_number": 179,
    "port_hints": [
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      "L23",
      "179"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_271",
    "name": "pin181",
    "pin_number": 181,
    "port_hints": [
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      "M2",
      "181"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_272",
    "name": "pin182",
    "pin_number": 182,
    "port_hints": [
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      "M3",
      "182"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_273",
    "name": "pin183",
    "pin_number": 183,
    "port_hints": [
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      "M5",
      "183"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_274",
    "name": "pin191",
    "pin_number": 191,
    "port_hints": [
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      "M19",
      "191"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_275",
    "name": "pin192",
    "pin_number": 192,
    "port_hints": [
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      "M21",
      "192"
    ],
    "source_component_id": "source_component_0",
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  {
    "type": "source_port",
    "source_port_id": "source_port_276",
    "name": "pin193",
    "pin_number": 193,
    "port_hints": [
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      "M22",
      "193"
    ],
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  {
    "type": "source_port",
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    "name": "pin194",
    "pin_number": 194,
    "port_hints": [
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      "M23",
      "194"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_278",
    "name": "pin195",
    "pin_number": 195,
    "port_hints": [
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      "N1",
      "195"
    ],
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  {
    "type": "source_port",
    "source_port_id": "source_port_279",
    "name": "pin196",
    "pin_number": 196,
    "port_hints": [
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      "N2",
      "196"
    ],
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    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "name": "pin197",
    "pin_number": 197,
    "port_hints": [
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      "N3",
      "197"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_281",
    "name": "pin198",
    "pin_number": 198,
    "port_hints": [
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      "N4",
      "198"
    ],
    "source_component_id": "source_component_0",
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  {
    "type": "source_port",
    "source_port_id": "source_port_282",
    "name": "pin199",
    "pin_number": 199,
    "port_hints": [
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      "N5",
      "199"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "name": "pin200",
    "pin_number": 200,
    "port_hints": [
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      "N6",
      "200"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_284",
    "name": "pin210",
    "pin_number": 210,
    "port_hints": [
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      "N19",
      "210"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_285",
    "name": "pin211",
    "pin_number": 211,
    "port_hints": [
      "pin211",
      "N20",
      "211"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_286",
    "name": "pin212",
    "pin_number": 212,
    "port_hints": [
      "pin212",
      "N21",
      "212"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_287",
    "name": "pin213",
    "pin_number": 213,
    "port_hints": [
      "pin213",
      "N22",
      "213"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_288",
    "name": "pin214",
    "pin_number": 214,
    "port_hints": [
      "pin214",
      "N23",
      "214"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_289",
    "name": "pin224",
    "pin_number": 224,
    "port_hints": [
      "pin224",
      "P22",
      "224"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_290",
    "name": "pin225",
    "pin_number": 225,
    "port_hints": [
      "pin225",
      "P23",
      "225"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_291",
    "name": "pin227",
    "pin_number": 227,
    "port_hints": [
      "pin227",
      "R2",
      "227"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_292",
    "name": "pin234",
    "pin_number": 234,
    "port_hints": [
      "pin234",
      "R22",
      "234"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_293",
    "name": "pin235",
    "pin_number": 235,
    "port_hints": [
      "pin235",
      "R23",
      "235"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_294",
    "name": "pin239",
    "pin_number": 239,
    "port_hints": [
      "pin239",
      "T4",
      "239"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_295",
    "name": "pin240",
    "pin_number": 240,
    "port_hints": [
      "pin240",
      "T5",
      "240"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_296",
    "name": "pin241",
    "pin_number": 241,
    "port_hints": [
      "pin241",
      "T6",
      "241"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_297",
    "name": "pin251",
    "pin_number": 251,
    "port_hints": [
      "pin251",
      "T20",
      "251"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_298",
    "name": "pin252",
    "pin_number": 252,
    "port_hints": [
      "pin252",
      "T21",
      "252"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_299",
    "name": "pin253",
    "pin_number": 253,
    "port_hints": [
      "pin253",
      "T22",
      "253"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_300",
    "name": "pin254",
    "pin_number": 254,
    "port_hints": [
      "pin254",
      "T23",
      "254"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_301",
    "name": "pin270",
    "pin_number": 270,
    "port_hints": [
      "pin270",
      "U22",
      "270"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_302",
    "name": "pin271",
    "pin_number": 271,
    "port_hints": [
      "pin271",
      "U23",
      "271"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_303",
    "name": "pin277",
    "pin_number": 277,
    "port_hints": [
      "pin277",
      "V6",
      "277"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_304",
    "name": "pin280",
    "pin_number": 280,
    "port_hints": [
      "pin280",
      "V20",
      "280"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_305",
    "name": "pin281",
    "pin_number": 281,
    "port_hints": [
      "pin281",
      "V21",
      "281"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_306",
    "name": "pin282",
    "pin_number": 282,
    "port_hints": [
      "pin282",
      "V22",
      "282"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_307",
    "name": "pin283",
    "pin_number": 283,
    "port_hints": [
      "pin283",
      "V23",
      "283"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_308",
    "name": "pin286",
    "pin_number": 286,
    "port_hints": [
      "pin286",
      "W6",
      "286"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_309",
    "name": "pin287",
    "pin_number": 287,
    "port_hints": [
      "pin287",
      "W8",
      "287"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_310",
    "name": "pin290",
    "pin_number": 290,
    "port_hints": [
      "pin290",
      "W11",
      "290"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_311",
    "name": "pin292",
    "pin_number": 292,
    "port_hints": [
      "pin292",
      "W13",
      "292"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_312",
    "name": "pin297",
    "pin_number": 297,
    "port_hints": [
      "pin297",
      "W22",
      "297"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_313",
    "name": "pin298",
    "pin_number": 298,
    "port_hints": [
      "pin298",
      "W23",
      "298"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_314",
    "name": "pin300",
    "pin_number": 300,
    "port_hints": [
      "pin300",
      "Y2",
      "300"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_315",
    "name": "pin301",
    "pin_number": 301,
    "port_hints": [
      "pin301",
      "Y3",
      "301"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_316",
    "name": "pin302",
    "pin_number": 302,
    "port_hints": [
      "pin302",
      "Y4",
      "302"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_317",
    "name": "pin303",
    "pin_number": 303,
    "port_hints": [
      "pin303",
      "Y6",
      "303"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_318",
    "name": "pin304",
    "pin_number": 304,
    "port_hints": [
      "pin304",
      "Y7",
      "304"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_319",
    "name": "pin305",
    "pin_number": 305,
    "port_hints": [
      "pin305",
      "Y8",
      "305"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_320",
    "name": "pin306",
    "pin_number": 306,
    "port_hints": [
      "pin306",
      "Y11",
      "306"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_321",
    "name": "pin307",
    "pin_number": 307,
    "port_hints": [
      "pin307",
      "Y13",
      "307"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_322",
    "name": "pin308",
    "pin_number": 308,
    "port_hints": [
      "pin308",
      "Y16",
      "308"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_323",
    "name": "pin309",
    "pin_number": 309,
    "port_hints": [
      "pin309",
      "Y17",
      "309"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_324",
    "name": "pin310",
    "pin_number": 310,
    "port_hints": [
      "pin310",
      "Y18",
      "310"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_325",
    "name": "pin313",
    "pin_number": 313,
    "port_hints": [
      "pin313",
      "Y22",
      "313"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_326",
    "name": "pin314",
    "pin_number": 314,
    "port_hints": [
      "pin314",
      "Y23",
      "314"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_327",
    "name": "pin315",
    "pin_number": 315,
    "port_hints": [
      "pin315",
      "AA1",
      "315"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_328",
    "name": "pin316",
    "pin_number": 316,
    "port_hints": [
      "pin316",
      "AA2",
      "316"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_329",
    "name": "pin318",
    "pin_number": 318,
    "port_hints": [
      "pin318",
      "AA6",
      "318"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_330",
    "name": "pin319",
    "pin_number": 319,
    "port_hints": [
      "pin319",
      "AA8",
      "319"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_331",
    "name": "pin320",
    "pin_number": 320,
    "port_hints": [
      "pin320",
      "AA11",
      "320"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_332",
    "name": "pin321",
    "pin_number": 321,
    "port_hints": [
      "pin321",
      "AA12",
      "321"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_333",
    "name": "pin322",
    "pin_number": 322,
    "port_hints": [
      "pin322",
      "AA13",
      "322"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_334",
    "name": "pin323",
    "pin_number": 323,
    "port_hints": [
      "pin323",
      "AA16",
      "323"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_335",
    "name": "pin324",
    "pin_number": 324,
    "port_hints": [
      "pin324",
      "AA18",
      "324"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_336",
    "name": "pin326",
    "pin_number": 326,
    "port_hints": [
      "pin326",
      "AA22",
      "326"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_337",
    "name": "pin327",
    "pin_number": 327,
    "port_hints": [
      "pin327",
      "AA23",
      "327"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_338",
    "name": "pin329",
    "pin_number": 329,
    "port_hints": [
      "pin329",
      "AB2",
      "329"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_339",
    "name": "pin330",
    "pin_number": 330,
    "port_hints": [
      "pin330",
      "AB3",
      "330"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_340",
    "name": "pin331",
    "pin_number": 331,
    "port_hints": [
      "pin331",
      "AB4",
      "331"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_341",
    "name": "pin332",
    "pin_number": 332,
    "port_hints": [
      "pin332",
      "AB5",
      "332"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_342",
    "name": "pin333",
    "pin_number": 333,
    "port_hints": [
      "pin333",
      "AB6",
      "333"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_343",
    "name": "pin335",
    "pin_number": 335,
    "port_hints": [
      "pin335",
      "AB8",
      "335"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_344",
    "name": "pin336",
    "pin_number": 336,
    "port_hints": [
      "pin336",
      "AB9",
      "336"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_345",
    "name": "pin337",
    "pin_number": 337,
    "port_hints": [
      "pin337",
      "AB10",
      "337"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_346",
    "name": "pin338",
    "pin_number": 338,
    "port_hints": [
      "pin338",
      "AB11",
      "338"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_347",
    "name": "pin339",
    "pin_number": 339,
    "port_hints": [
      "pin339",
      "AB12",
      "339"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_348",
    "name": "pin340",
    "pin_number": 340,
    "port_hints": [
      "pin340",
      "AB13",
      "340"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_349",
    "name": "pin341",
    "pin_number": 341,
    "port_hints": [
      "pin341",
      "AB14",
      "341"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_350",
    "name": "pin342",
    "pin_number": 342,
    "port_hints": [
      "pin342",
      "AB15",
      "342"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_351",
    "name": "pin343",
    "pin_number": 343,
    "port_hints": [
      "pin343",
      "AB16",
      "343"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_352",
    "name": "pin344",
    "pin_number": 344,
    "port_hints": [
      "pin344",
      "AB17",
      "344"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_353",
    "name": "pin345",
    "pin_number": 345,
    "port_hints": [
      "pin345",
      "AB18",
      "345"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_354",
    "name": "pin346",
    "pin_number": 346,
    "port_hints": [
      "pin346",
      "AB19",
      "346"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_355",
    "name": "pin347",
    "pin_number": 347,
    "port_hints": [
      "pin347",
      "AB20",
      "347"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_356",
    "name": "pin349",
    "pin_number": 349,
    "port_hints": [
      "pin349",
      "AB22",
      "349"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_357",
    "name": "pin353",
    "pin_number": 353,
    "port_hints": [
      "pin353",
      "AC3",
      "353"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_358",
    "name": "pin354",
    "pin_number": 354,
    "port_hints": [
      "pin354",
      "AC4",
      "354"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_359",
    "name": "pin355",
    "pin_number": 355,
    "port_hints": [
      "pin355",
      "AC5",
      "355"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_360",
    "name": "pin356",
    "pin_number": 356,
    "port_hints": [
      "pin356",
      "AC6",
      "356"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_361",
    "name": "pin357",
    "pin_number": 357,
    "port_hints": [
      "pin357",
      "AC7",
      "357"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_362",
    "name": "pin358",
    "pin_number": 358,
    "port_hints": [
      "pin358",
      "AC8",
      "358"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_363",
    "name": "pin359",
    "pin_number": 359,
    "port_hints": [
      "pin359",
      "AC9",
      "359"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_364",
    "name": "pin360",
    "pin_number": 360,
    "port_hints": [
      "pin360",
      "AC10",
      "360"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_365",
    "name": "pin362",
    "pin_number": 362,
    "port_hints": [
      "pin362",
      "AC12",
      "362"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_366",
    "name": "pin363",
    "pin_number": 363,
    "port_hints": [
      "pin363",
      "AC13",
      "363"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_367",
    "name": "pin365",
    "pin_number": 365,
    "port_hints": [
      "pin365",
      "AC15",
      "365"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_368",
    "name": "pin366",
    "pin_number": 366,
    "port_hints": [
      "pin366",
      "AC16",
      "366"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_369",
    "name": "pin367",
    "pin_number": 367,
    "port_hints": [
      "pin367",
      "AC17",
      "367"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_370",
    "name": "pin368",
    "pin_number": 368,
    "port_hints": [
      "pin368",
      "AC18",
      "368"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_371",
    "name": "pin370",
    "pin_number": 370,
    "port_hints": [
      "pin370",
      "AC20",
      "370"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_372",
    "name": "pin371",
    "pin_number": 371,
    "port_hints": [
      "pin371",
      "AC21",
      "371"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_0",
    "ftype": "simple_chip",
    "name": "U1",
    "manufacturer_part_number": "AM62L32BOGHAANBR",
    "source_group_id": "source_group_0",
    "internally_connected_source_port_ids": [
      [
        "source_port_0",
        "source_port_1",
        "source_port_2",
        "source_port_3",
        "source_port_4",
        "source_port_5",
        "source_port_6",
        "source_port_7",
        "source_port_8",
        "source_port_9",
        "source_port_10",
        "source_port_11",
        "source_port_12",
        "source_port_13",
        "source_port_14",
        "source_port_15",
        "source_port_16",
        "source_port_17",
        "source_port_18",
        "source_port_19",
        "source_port_20",
        "source_port_21",
        "source_port_22",
        "source_port_23",
        "source_port_24",
        "source_port_25",
        "source_port_26",
        "source_port_27",
        "source_port_28",
        "source_port_29",
        "source_port_30",
        "source_port_31",
        "source_port_32",
        "source_port_33",
        "source_port_34",
        "source_port_35",
        "source_port_36",
        "source_port_37",
        "source_port_38",
        "source_port_39",
        "source_port_40",
        "source_port_41",
        "source_port_42",
        "source_port_43",
        "source_port_44",
        "source_port_45",
        "source_port_46",
        "source_port_47",
        "source_port_48",
        "source_port_49",
        "source_port_50",
        "source_port_51",
        "source_port_52",
        "source_port_53",
        "source_port_54",
        "source_port_55",
        "source_port_56",
        "source_port_57",
        "source_port_58",
        "source_port_59",
        "source_port_60",
        "source_port_61",
        "source_port_62",
        "source_port_63",
        "source_port_64",
        "source_port_65",
        "source_port_66",
        "source_port_67",
        "source_port_68",
        "source_port_69",
        "source_port_70",
        "source_port_71",
        "source_port_72",
        "source_port_73",
        "source_port_74",
        "source_port_75",
        "source_port_76",
        "source_port_77",
        "source_port_78",
        "source_port_79",
        "source_port_80",
        "source_port_81",
        "source_port_82",
        "source_port_83",
        "source_port_84",
        "source_port_85",
        "source_port_86",
        "source_port_87",
        "source_port_88",
        "source_port_89",
        "source_port_90",
        "source_port_91",
        "source_port_92",
        "source_port_93",
        "source_port_94",
        "source_port_95",
        "source_port_96"
      ],
      [
        "source_port_97",
        "source_port_98",
        "source_port_99",
        "source_port_100",
        "source_port_101",
        "source_port_102",
        "source_port_103",
        "source_port_104",
        "source_port_105",
        "source_port_106",
        "source_port_107",
        "source_port_108",
        "source_port_109",
        "source_port_110"
      ],
      [
        "source_port_112",
        "source_port_113",
        "source_port_114",
        "source_port_115",
        "source_port_116"
      ],
      [
        "source_port_124",
        "source_port_125"
      ],
      [
        "source_port_126",
        "source_port_127"
      ]
    ]
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_373",
    "name": "A3",
    "pin_number": 3,
    "port_hints": [
      "A3",
      "VSS",
      "pin3",
      "3"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_374",
    "name": "A10",
    "pin_number": 8,
    "port_hints": [
      "A10",
      "VSS",
      "pin8",
      "8"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_375",
    "name": "C1",
    "pin_number": 21,
    "port_hints": [
      "C1",
      "VSS",
      "pin21",
      "21"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_376",
    "name": "C5",
    "pin_number": 25,
    "port_hints": [
      "C5",
      "VSS",
      "pin25",
      "25"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_377",
    "name": "C8",
    "pin_number": 26,
    "port_hints": [
      "C8",
      "VSS",
      "pin26",
      "26"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_378",
    "name": "C12",
    "pin_number": 30,
    "port_hints": [
      "C12",
      "VSS",
      "pin30",
      "30"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_379",
    "name": "D2",
    "pin_number": 32,
    "port_hints": [
      "D2",
      "VSS",
      "pin32",
      "32"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_380",
    "name": "D4",
    "pin_number": 34,
    "port_hints": [
      "D4",
      "VSS",
      "pin34",
      "34"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_381",
    "name": "D9",
    "pin_number": 37,
    "port_hints": [
      "D9",
      "VSS",
      "pin37",
      "37"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_382",
    "name": "D11",
    "pin_number": 39,
    "port_hints": [
      "D11",
      "VSS",
      "pin39",
      "39"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_383",
    "name": "E1",
    "pin_number": 41,
    "port_hints": [
      "E1",
      "VSS",
      "pin41",
      "41"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_384",
    "name": "E5",
    "pin_number": 45,
    "port_hints": [
      "E5",
      "VSS",
      "pin45",
      "45"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_385",
    "name": "E8",
    "pin_number": 46,
    "port_hints": [
      "E8",
      "VSS",
      "pin46",
      "46"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_386",
    "name": "E12",
    "pin_number": 50,
    "port_hints": [
      "E12",
      "VSS",
      "pin50",
      "50"
    ],
    "source_component_id": "source_component_1",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_387",
    "name": "G1",
    "pin_number": 61,
    "port_hints": [
      "G1",
      "VSS",
      "pin61",
      "61"
    ],
    "source_component_id": "source_component_1",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_388",
    "name": "G3",
    "pin_number": 63,
    "port_hints": [
      "G3",
      "VSS",
      "pin63",
      "63"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_389",
    "name": "G5",
    "pin_number": 65,
    "port_hints": [
      "G5",
      "VSS",
      "pin65",
      "65"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_390",
    "name": "G8",
    "pin_number": 66,
    "port_hints": [
      "G8",
      "VSS",
      "pin66",
      "66"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_391",
    "name": "G10",
    "pin_number": 68,
    "port_hints": [
      "G10",
      "VSS",
      "pin68",
      "68"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_392",
    "name": "G12",
    "pin_number": 70,
    "port_hints": [
      "G12",
      "VSS",
      "pin70",
      "70"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_393",
    "name": "J1",
    "pin_number": 81,
    "port_hints": [
      "J1",
      "VSS",
      "pin81",
      "81"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_394",
    "name": "J3",
    "pin_number": 83,
    "port_hints": [
      "J3",
      "VSS",
      "pin83",
      "83"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_395",
    "name": "J10",
    "pin_number": 88,
    "port_hints": [
      "J10",
      "VSS",
      "pin88",
      "88"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_396",
    "name": "J12",
    "pin_number": 90,
    "port_hints": [
      "J12",
      "VSS",
      "pin90",
      "90"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_397",
    "name": "K2",
    "pin_number": 92,
    "port_hints": [
      "K2",
      "VSS",
      "pin92",
      "92"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_398",
    "name": "K4",
    "pin_number": 94,
    "port_hints": [
      "K4",
      "VSS",
      "pin94",
      "94"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_399",
    "name": "K9",
    "pin_number": 97,
    "port_hints": [
      "K9",
      "VSS",
      "pin97",
      "97"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_400",
    "name": "K11",
    "pin_number": 99,
    "port_hints": [
      "K11",
      "VSS",
      "pin99",
      "99"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_401",
    "name": "N2",
    "pin_number": 102,
    "port_hints": [
      "N2",
      "VSS",
      "pin102",
      "102"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_402",
    "name": "N4",
    "pin_number": 104,
    "port_hints": [
      "N4",
      "VSS",
      "pin104",
      "104"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_403",
    "name": "N9",
    "pin_number": 107,
    "port_hints": [
      "N9",
      "VSS",
      "pin107",
      "107"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_404",
    "name": "N11",
    "pin_number": 109,
    "port_hints": [
      "N11",
      "VSS",
      "pin109",
      "109"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_405",
    "name": "P1",
    "pin_number": 111,
    "port_hints": [
      "P1",
      "VSS",
      "pin111",
      "111"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_406",
    "name": "P3",
    "pin_number": 113,
    "port_hints": [
      "P3",
      "VSS",
      "pin113",
      "113"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_407",
    "name": "P10",
    "pin_number": 118,
    "port_hints": [
      "P10",
      "VSS",
      "pin118",
      "118"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_408",
    "name": "P12",
    "pin_number": 120,
    "port_hints": [
      "P12",
      "VSS",
      "pin120",
      "120"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_409",
    "name": "T1",
    "pin_number": 131,
    "port_hints": [
      "T1",
      "VSS",
      "pin131",
      "131"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_410",
    "name": "T3",
    "pin_number": 133,
    "port_hints": [
      "T3",
      "VSS",
      "pin133",
      "133"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_411",
    "name": "T5",
    "pin_number": 135,
    "port_hints": [
      "T5",
      "VSS",
      "pin135",
      "135"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_412",
    "name": "T8",
    "pin_number": 136,
    "port_hints": [
      "T8",
      "VSS",
      "pin136",
      "136"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_413",
    "name": "T10",
    "pin_number": 138,
    "port_hints": [
      "T10",
      "VSS",
      "pin138",
      "138"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_414",
    "name": "T12",
    "pin_number": 140,
    "port_hints": [
      "T12",
      "VSS",
      "pin140",
      "140"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_415",
    "name": "V1",
    "pin_number": 151,
    "port_hints": [
      "V1",
      "VSS",
      "pin151",
      "151"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_416",
    "name": "V5",
    "pin_number": 155,
    "port_hints": [
      "V5",
      "VSS",
      "pin155",
      "155"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_417",
    "name": "V8",
    "pin_number": 156,
    "port_hints": [
      "V8",
      "VSS",
      "pin156",
      "156"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_418",
    "name": "V12",
    "pin_number": 160,
    "port_hints": [
      "V12",
      "VSS",
      "pin160",
      "160"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_419",
    "name": "W2",
    "pin_number": 162,
    "port_hints": [
      "W2",
      "VSS",
      "pin162",
      "162"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_420",
    "name": "W4",
    "pin_number": 164,
    "port_hints": [
      "W4",
      "VSS",
      "pin164",
      "164"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_421",
    "name": "W9",
    "pin_number": 167,
    "port_hints": [
      "W9",
      "VSS",
      "pin167",
      "167"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_422",
    "name": "W11",
    "pin_number": 169,
    "port_hints": [
      "W11",
      "VSS",
      "pin169",
      "169"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_423",
    "name": "Y1",
    "pin_number": 171,
    "port_hints": [
      "Y1",
      "VSS",
      "pin171",
      "171"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_424",
    "name": "Y5",
    "pin_number": 175,
    "port_hints": [
      "Y5",
      "VSS",
      "pin175",
      "175"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_425",
    "name": "Y8",
    "pin_number": 176,
    "port_hints": [
      "Y8",
      "VSS",
      "pin176",
      "176"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_426",
    "name": "Y12",
    "pin_number": 180,
    "port_hints": [
      "Y12",
      "VSS",
      "pin180",
      "180"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_427",
    "name": "AB3",
    "pin_number": 193,
    "port_hints": [
      "AB3",
      "VSS",
      "pin193",
      "193"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_428",
    "name": "AB5",
    "pin_number": 195,
    "port_hints": [
      "AB5",
      "VSS",
      "pin195",
      "195"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_429",
    "name": "AB8",
    "pin_number": 196,
    "port_hints": [
      "AB8",
      "VSS",
      "pin196",
      "196"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_430",
    "name": "AB10",
    "pin_number": 198,
    "port_hints": [
      "AB10",
      "VSS",
      "pin198",
      "198"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_431",
    "name": "B3",
    "pin_number": 13,
    "port_hints": [
      "B3",
      "VDDQ",
      "pin13",
      "13"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_432",
    "name": "B5",
    "pin_number": 15,
    "port_hints": [
      "B5",
      "VDDQ",
      "pin15",
      "15"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_433",
    "name": "B8",
    "pin_number": 16,
    "port_hints": [
      "B8",
      "VDDQ",
      "pin16",
      "16"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_434",
    "name": "B10",
    "pin_number": 18,
    "port_hints": [
      "B10",
      "VDDQ",
      "pin18",
      "18"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_435",
    "name": "D1",
    "pin_number": 31,
    "port_hints": [
      "D1",
      "VDDQ",
      "pin31",
      "31"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_436",
    "name": "D5",
    "pin_number": 35,
    "port_hints": [
      "D5",
      "VDDQ",
      "pin35",
      "35"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_437",
    "name": "D8",
    "pin_number": 36,
    "port_hints": [
      "D8",
      "VDDQ",
      "pin36",
      "36"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_438",
    "name": "D12",
    "pin_number": 40,
    "port_hints": [
      "D12",
      "VDDQ",
      "pin40",
      "40"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_439",
    "name": "F3",
    "pin_number": 53,
    "port_hints": [
      "F3",
      "VDDQ",
      "pin53",
      "53"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_440",
    "name": "F10",
    "pin_number": 58,
    "port_hints": [
      "F10",
      "VDDQ",
      "pin58",
      "58"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_441",
    "name": "U3",
    "pin_number": 143,
    "port_hints": [
      "U3",
      "VDDQ",
      "pin143",
      "143"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_442",
    "name": "U10",
    "pin_number": 148,
    "port_hints": [
      "U10",
      "VDDQ",
      "pin148",
      "148"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_443",
    "name": "W1",
    "pin_number": 161,
    "port_hints": [
      "W1",
      "VDDQ",
      "pin161",
      "161"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_444",
    "name": "W5",
    "pin_number": 165,
    "port_hints": [
      "W5",
      "VDDQ",
      "pin165",
      "165"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_445",
    "name": "W8",
    "pin_number": 166,
    "port_hints": [
      "W8",
      "VDDQ",
      "pin166",
      "166"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_446",
    "name": "W12",
    "pin_number": 170,
    "port_hints": [
      "W12",
      "VDDQ",
      "pin170",
      "170"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_447",
    "name": "AA3",
    "pin_number": 183,
    "port_hints": [
      "AA3",
      "VDDQ",
      "pin183",
      "183"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_448",
    "name": "AA5",
    "pin_number": 185,
    "port_hints": [
      "AA5",
      "VDDQ",
      "pin185",
      "185"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_449",
    "name": "AA8",
    "pin_number": 186,
    "port_hints": [
      "AA8",
      "VDDQ",
      "pin186",
      "186"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_450",
    "name": "AA10",
    "pin_number": 188,
    "port_hints": [
      "AA10",
      "VDDQ",
      "pin188",
      "188"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_451",
    "name": "A4",
    "pin_number": 4,
    "port_hints": [
      "A4",
      "VDD2",
      "pin4",
      "4"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_452",
    "name": "A9",
    "pin_number": 7,
    "port_hints": [
      "A9",
      "VDD2",
      "pin7",
      "7"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_453",
    "name": "F5",
    "pin_number": 55,
    "port_hints": [
      "F5",
      "VDD2",
      "pin55",
      "55"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_454",
    "name": "F8",
    "pin_number": 56,
    "port_hints": [
      "F8",
      "VDD2",
      "pin56",
      "56"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_455",
    "name": "H1",
    "pin_number": 71,
    "port_hints": [
      "H1",
      "VDD2",
      "pin71",
      "71"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_456",
    "name": "H5",
    "pin_number": 75,
    "port_hints": [
      "H5",
      "VDD2",
      "pin75",
      "75"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_457",
    "name": "H8",
    "pin_number": 76,
    "port_hints": [
      "H8",
      "VDD2",
      "pin76",
      "76"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_458",
    "name": "H12",
    "pin_number": 80,
    "port_hints": [
      "H12",
      "VDD2",
      "pin80",
      "80"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_459",
    "name": "K1",
    "pin_number": 91,
    "port_hints": [
      "K1",
      "VDD2",
      "pin91",
      "91"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_460",
    "name": "K3",
    "pin_number": 93,
    "port_hints": [
      "K3",
      "VDD2",
      "pin93",
      "93"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_461",
    "name": "K10",
    "pin_number": 98,
    "port_hints": [
      "K10",
      "VDD2",
      "pin98",
      "98"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_462",
    "name": "K12",
    "pin_number": 100,
    "port_hints": [
      "K12",
      "VDD2",
      "pin100",
      "100"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_463",
    "name": "N1",
    "pin_number": 101,
    "port_hints": [
      "N1",
      "VDD2",
      "pin101",
      "101"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_464",
    "name": "N3",
    "pin_number": 103,
    "port_hints": [
      "N3",
      "VDD2",
      "pin103",
      "103"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_465",
    "name": "N10",
    "pin_number": 108,
    "port_hints": [
      "N10",
      "VDD2",
      "pin108",
      "108"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_466",
    "name": "N12",
    "pin_number": 110,
    "port_hints": [
      "N12",
      "VDD2",
      "pin110",
      "110"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_467",
    "name": "R1",
    "pin_number": 121,
    "port_hints": [
      "R1",
      "VDD2",
      "pin121",
      "121"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_468",
    "name": "R5",
    "pin_number": 125,
    "port_hints": [
      "R5",
      "VDD2",
      "pin125",
      "125"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_469",
    "name": "R8",
    "pin_number": 126,
    "port_hints": [
      "R8",
      "VDD2",
      "pin126",
      "126"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_470",
    "name": "R12",
    "pin_number": 130,
    "port_hints": [
      "R12",
      "VDD2",
      "pin130",
      "130"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_471",
    "name": "U5",
    "pin_number": 145,
    "port_hints": [
      "U5",
      "VDD2",
      "pin145",
      "145"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_472",
    "name": "U8",
    "pin_number": 146,
    "port_hints": [
      "U8",
      "VDD2",
      "pin146",
      "146"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_473",
    "name": "AB4",
    "pin_number": 194,
    "port_hints": [
      "AB4",
      "VDD2",
      "pin194",
      "194"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_474",
    "name": "AB9",
    "pin_number": 197,
    "port_hints": [
      "AB9",
      "VDD2",
      "pin197",
      "197"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_475",
    "name": "F1",
    "pin_number": 51,
    "port_hints": [
      "F1",
      "VDD1",
      "pin51",
      "51"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_476",
    "name": "F12",
    "pin_number": 60,
    "port_hints": [
      "F12",
      "VDD1",
      "pin60",
      "60"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_477",
    "name": "G4",
    "pin_number": 64,
    "port_hints": [
      "G4",
      "VDD1",
      "pin64",
      "64"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_478",
    "name": "G9",
    "pin_number": 67,
    "port_hints": [
      "G9",
      "VDD1",
      "pin67",
      "67"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_479",
    "name": "T4",
    "pin_number": 134,
    "port_hints": [
      "T4",
      "VDD1",
      "pin134",
      "134"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_480",
    "name": "T9",
    "pin_number": 137,
    "port_hints": [
      "T9",
      "VDD1",
      "pin137",
      "137"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_481",
    "name": "U1",
    "pin_number": 141,
    "port_hints": [
      "U1",
      "VDD1",
      "pin141",
      "141"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_482",
    "name": "U12",
    "pin_number": 150,
    "port_hints": [
      "U12",
      "VDD1",
      "pin150",
      "150"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_483",
    "name": "H2",
    "pin_number": 72,
    "port_hints": [
      "H2",
      "CA0",
      "pin72",
      "72"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net19"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_484",
    "name": "J2",
    "pin_number": 82,
    "port_hints": [
      "J2",
      "CA1",
      "pin82",
      "82"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net20"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_485",
    "name": "H9",
    "pin_number": 77,
    "port_hints": [
      "H9",
      "CA2",
      "pin77",
      "77"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net21"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_486",
    "name": "H10",
    "pin_number": 78,
    "port_hints": [
      "H10",
      "CA3",
      "pin78",
      "78"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net22"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_487",
    "name": "H11",
    "pin_number": 79,
    "port_hints": [
      "H11",
      "CA4",
      "pin79",
      "79"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net23"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_488",
    "name": "J11",
    "pin_number": 89,
    "port_hints": [
      "J11",
      "CA5",
      "pin89",
      "89"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net24"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_489",
    "name": "H4",
    "pin_number": 74,
    "port_hints": [
      "H4",
      "CS",
      "pin74",
      "74"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net25"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_490",
    "name": "J4",
    "pin_number": 84,
    "port_hints": [
      "J4",
      "CKE",
      "pin84",
      "84"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net26"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_491",
    "name": "J8",
    "pin_number": 86,
    "port_hints": [
      "J8",
      "CK_t",
      "pin86",
      "86"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net27"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_492",
    "name": "J9",
    "pin_number": 87,
    "port_hints": [
      "J9",
      "CK_c",
      "pin87",
      "87"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net28"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_493",
    "name": "D3",
    "pin_number": 33,
    "port_hints": [
      "D3",
      "DQS0_t",
      "pin33",
      "33"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net29"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_494",
    "name": "E3",
    "pin_number": 43,
    "port_hints": [
      "E3",
      "DQS0_c",
      "pin43",
      "43"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net30"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_495",
    "name": "D10",
    "pin_number": 38,
    "port_hints": [
      "D10",
      "DQS1_t",
      "pin38",
      "38"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net31"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_496",
    "name": "E10",
    "pin_number": 48,
    "port_hints": [
      "E10",
      "DQS1_c",
      "pin48",
      "48"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net32"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_497",
    "name": "T11",
    "pin_number": 139,
    "port_hints": [
      "T11",
      "RESET_n",
      "pin139",
      "139"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net33"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_498",
    "name": "C3",
    "pin_number": 23,
    "port_hints": [
      "C3",
      "DMI0",
      "pin23",
      "23"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net34"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_499",
    "name": "C10",
    "pin_number": 28,
    "port_hints": [
      "C10",
      "DMI1",
      "pin28",
      "28"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net35"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_500",
    "name": "B2",
    "pin_number": 12,
    "port_hints": [
      "B2",
      "DQ0",
      "pin12",
      "12"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net3"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_501",
    "name": "B4",
    "pin_number": 14,
    "port_hints": [
      "B4",
      "DQ7",
      "pin14",
      "14"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net10"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_502",
    "name": "B9",
    "pin_number": 17,
    "port_hints": [
      "B9",
      "DQ15",
      "pin17",
      "17"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net18"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_503",
    "name": "B11",
    "pin_number": 19,
    "port_hints": [
      "B11",
      "DQ8",
      "pin19",
      "19"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net11"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_504",
    "name": "C2",
    "pin_number": 22,
    "port_hints": [
      "C2",
      "DQ1",
      "pin22",
      "22"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_505",
    "name": "C4",
    "pin_number": 24,
    "port_hints": [
      "C4",
      "DQ6",
      "pin24",
      "24"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net9"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_506",
    "name": "C9",
    "pin_number": 27,
    "port_hints": [
      "C9",
      "DQ14",
      "pin27",
      "27"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net17"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_507",
    "name": "C11",
    "pin_number": 29,
    "port_hints": [
      "C11",
      "DQ9",
      "pin29",
      "29"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net12"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_508",
    "name": "E2",
    "pin_number": 42,
    "port_hints": [
      "E2",
      "DQ2",
      "pin42",
      "42"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net5"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_509",
    "name": "E4",
    "pin_number": 44,
    "port_hints": [
      "E4",
      "DQ5",
      "pin44",
      "44"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net8"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_510",
    "name": "E9",
    "pin_number": 47,
    "port_hints": [
      "E9",
      "DQ13",
      "pin47",
      "47"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_511",
    "name": "E11",
    "pin_number": 49,
    "port_hints": [
      "E11",
      "DQ10",
      "pin49",
      "49"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net13"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_512",
    "name": "F2",
    "pin_number": 52,
    "port_hints": [
      "F2",
      "DQ3",
      "pin52",
      "52"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net6"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_513",
    "name": "F4",
    "pin_number": 54,
    "port_hints": [
      "F4",
      "DQ4",
      "pin54",
      "54"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net7"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_514",
    "name": "F9",
    "pin_number": 57,
    "port_hints": [
      "F9",
      "DQ12",
      "pin57",
      "57"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net15"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_515",
    "name": "F11",
    "pin_number": 59,
    "port_hints": [
      "F11",
      "DQ11",
      "pin59",
      "59"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net14"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_516",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "A1",
      "1"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_517",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "A2",
      "2"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_518",
    "name": "pin5",
    "pin_number": 5,
    "port_hints": [
      "pin5",
      "A5",
      "5"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_519",
    "name": "pin6",
    "pin_number": 6,
    "port_hints": [
      "pin6",
      "A8",
      "6"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_520",
    "name": "pin9",
    "pin_number": 9,
    "port_hints": [
      "pin9",
      "A11",
      "9"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_521",
    "name": "pin10",
    "pin_number": 10,
    "port_hints": [
      "pin10",
      "A12",
      "10"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_522",
    "name": "pin11",
    "pin_number": 11,
    "port_hints": [
      "pin11",
      "B1",
      "11"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_523",
    "name": "pin20",
    "pin_number": 20,
    "port_hints": [
      "pin20",
      "B12",
      "20"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_524",
    "name": "pin62",
    "pin_number": 62,
    "port_hints": [
      "pin62",
      "G2",
      "62"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_525",
    "name": "pin69",
    "pin_number": 69,
    "port_hints": [
      "pin69",
      "G11",
      "69"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_526",
    "name": "pin73",
    "pin_number": 73,
    "port_hints": [
      "pin73",
      "H3",
      "73"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_527",
    "name": "pin85",
    "pin_number": 85,
    "port_hints": [
      "pin85",
      "J5",
      "85"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_528",
    "name": "pin95",
    "pin_number": 95,
    "port_hints": [
      "pin95",
      "K5",
      "95"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_529",
    "name": "pin96",
    "pin_number": 96,
    "port_hints": [
      "pin96",
      "K8",
      "96"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_530",
    "name": "pin105",
    "pin_number": 105,
    "port_hints": [
      "pin105",
      "N5",
      "105"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_531",
    "name": "pin106",
    "pin_number": 106,
    "port_hints": [
      "pin106",
      "N8",
      "106"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_532",
    "name": "pin112",
    "pin_number": 112,
    "port_hints": [
      "pin112",
      "P2",
      "112"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_533",
    "name": "pin114",
    "pin_number": 114,
    "port_hints": [
      "pin114",
      "P4",
      "114"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_534",
    "name": "pin115",
    "pin_number": 115,
    "port_hints": [
      "pin115",
      "P5",
      "115"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_535",
    "name": "pin116",
    "pin_number": 116,
    "port_hints": [
      "pin116",
      "P8",
      "116"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_536",
    "name": "pin117",
    "pin_number": 117,
    "port_hints": [
      "pin117",
      "P9",
      "117"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_537",
    "name": "pin119",
    "pin_number": 119,
    "port_hints": [
      "pin119",
      "P11",
      "119"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_538",
    "name": "pin122",
    "pin_number": 122,
    "port_hints": [
      "pin122",
      "R2",
      "122"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_539",
    "name": "pin123",
    "pin_number": 123,
    "port_hints": [
      "pin123",
      "R3",
      "123"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_540",
    "name": "pin124",
    "pin_number": 124,
    "port_hints": [
      "pin124",
      "R4",
      "124"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_541",
    "name": "pin127",
    "pin_number": 127,
    "port_hints": [
      "pin127",
      "R9",
      "127"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_542",
    "name": "pin128",
    "pin_number": 128,
    "port_hints": [
      "pin128",
      "R10",
      "128"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_543",
    "name": "pin129",
    "pin_number": 129,
    "port_hints": [
      "pin129",
      "R11",
      "129"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_544",
    "name": "pin132",
    "pin_number": 132,
    "port_hints": [
      "pin132",
      "T2",
      "132"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_545",
    "name": "pin142",
    "pin_number": 142,
    "port_hints": [
      "pin142",
      "U2",
      "142"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_546",
    "name": "pin144",
    "pin_number": 144,
    "port_hints": [
      "pin144",
      "U4",
      "144"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_547",
    "name": "pin147",
    "pin_number": 147,
    "port_hints": [
      "pin147",
      "U9",
      "147"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_548",
    "name": "pin149",
    "pin_number": 149,
    "port_hints": [
      "pin149",
      "U11",
      "149"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_549",
    "name": "pin152",
    "pin_number": 152,
    "port_hints": [
      "pin152",
      "V2",
      "152"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_550",
    "name": "pin153",
    "pin_number": 153,
    "port_hints": [
      "pin153",
      "V3",
      "153"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_551",
    "name": "pin154",
    "pin_number": 154,
    "port_hints": [
      "pin154",
      "V4",
      "154"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_552",
    "name": "pin157",
    "pin_number": 157,
    "port_hints": [
      "pin157",
      "V9",
      "157"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_553",
    "name": "pin158",
    "pin_number": 158,
    "port_hints": [
      "pin158",
      "V10",
      "158"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_554",
    "name": "pin159",
    "pin_number": 159,
    "port_hints": [
      "pin159",
      "V11",
      "159"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_555",
    "name": "pin163",
    "pin_number": 163,
    "port_hints": [
      "pin163",
      "W3",
      "163"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_556",
    "name": "pin168",
    "pin_number": 168,
    "port_hints": [
      "pin168",
      "W10",
      "168"
    ],
    "source_component_id": "source_component_1",
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  {
    "type": "source_port",
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  {
    "type": "source_port",
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  {
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  {
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  {
    "type": "source_component_internal_connection",
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      "source_port_50",
      "source_port_51",
      "source_port_52",
      "source_port_53",
      "source_port_54",
      "source_port_55",
      "source_port_56",
      "source_port_57",
      "source_port_58",
      "source_port_59",
      "source_port_60",
      "source_port_61",
      "source_port_62",
      "source_port_63",
      "source_port_64",
      "source_port_65",
      "source_port_66",
      "source_port_67",
      "source_port_68",
      "source_port_69",
      "source_port_70",
      "source_port_71",
      "source_port_72",
      "source_port_73",
      "source_port_74",
      "source_port_75",
      "source_port_76",
      "source_port_77",
      "source_port_78",
      "source_port_79",
      "source_port_80",
      "source_port_81",
      "source_port_82",
      "source_port_83",
      "source_port_84",
      "source_port_85",
      "source_port_86",
      "source_port_87",
      "source_port_88",
      "source_port_89",
      "source_port_90",
      "source_port_91",
      "source_port_92",
      "source_port_93",
      "source_port_94",
      "source_port_95",
      "source_port_96"
    ]
  },
  {
    "type": "source_component_internal_connection",
    "source_component_internal_connection_id": "source_component_internal_connection_1",
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_port_ids": [
      "source_port_97",
      "source_port_98",
      "source_port_99",
      "source_port_100",
      "source_port_101",
      "source_port_102",
      "source_port_103",
      "source_port_104",
      "source_port_105",
      "source_port_106",
      "source_port_107",
      "source_port_108",
      "source_port_109",
      "source_port_110"
    ]
  },
  {
    "type": "source_component_internal_connection",
    "source_component_internal_connection_id": "source_component_internal_connection_2",
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_port_ids": [
      "source_port_112",
      "source_port_113",
      "source_port_114",
      "source_port_115",
      "source_port_116"
    ]
  },
  {
    "type": "source_component_internal_connection",
    "source_component_internal_connection_id": "source_component_internal_connection_3",
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_port_ids": [
      "source_port_124",
      "source_port_125"
    ]
  },
  {
    "type": "source_component_internal_connection",
    "source_component_internal_connection_id": "source_component_internal_connection_4",
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_port_ids": [
      "source_port_126",
      "source_port_127"
    ]
  },
  {
    "type": "source_component_internal_connection",
    "source_component_internal_connection_id": "source_component_internal_connection_5",
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_port_ids": [
      "source_port_373",
      "source_port_374",
      "source_port_375",
      "source_port_376",
      "source_port_377",
      "source_port_378",
      "source_port_379",
      "source_port_380",
      "source_port_381",
      "source_port_382",
      "source_port_383",
      "source_port_384",
      "source_port_385",
      "source_port_386",
      "source_port_387",
      "source_port_388",
      "source_port_389",
      "source_port_390",
      "source_port_391",
      "source_port_392",
      "source_port_393",
      "source_port_394",
      "source_port_395",
      "source_port_396",
      "source_port_397",
      "source_port_398",
      "source_port_399",
      "source_port_400",
      "source_port_401",
      "source_port_402",
      "source_port_403",
      "source_port_404",
      "source_port_405",
      "source_port_406",
      "source_port_407",
      "source_port_408",
      "source_port_409",
      "source_port_410",
      "source_port_411",
      "source_port_412",
      "source_port_413",
      "source_port_414",
      "source_port_415",
      "source_port_416",
      "source_port_417",
      "source_port_418",
      "source_port_419",
      "source_port_420",
      "source_port_421",
      "source_port_422",
      "source_port_423",
      "source_port_424",
      "source_port_425",
      "source_port_426",
      "source_port_427",
      "source_port_428",
      "source_port_429",
      "source_port_430"
    ]
  },
  {
    "type": "source_component_internal_connection",
    "source_component_internal_connection_id": "source_component_internal_connection_6",
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_port_ids": [
      "source_port_431",
      "source_port_432",
      "source_port_433",
      "source_port_434",
      "source_port_435",
      "source_port_436",
      "source_port_437",
      "source_port_438",
      "source_port_439",
      "source_port_440",
      "source_port_441",
      "source_port_442",
      "source_port_443",
      "source_port_444",
      "source_port_445",
      "source_port_446",
      "source_port_447",
      "source_port_448",
      "source_port_449",
      "source_port_450"
    ]
  },
  {
    "type": "source_component_internal_connection",
    "source_component_internal_connection_id": "source_component_internal_connection_7",
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_port_ids": [
      "source_port_451",
      "source_port_452",
      "source_port_453",
      "source_port_454",
      "source_port_455",
      "source_port_456",
      "source_port_457",
      "source_port_458",
      "source_port_459",
      "source_port_460",
      "source_port_461",
      "source_port_462",
      "source_port_463",
      "source_port_464",
      "source_port_465",
      "source_port_466",
      "source_port_467",
      "source_port_468",
      "source_port_469",
      "source_port_470",
      "source_port_471",
      "source_port_472",
      "source_port_473",
      "source_port_474"
    ]
  },
  {
    "type": "source_component_internal_connection",
    "source_component_internal_connection_id": "source_component_internal_connection_8",
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_port_ids": [
      "source_port_475",
      "source_port_476",
      "source_port_477",
      "source_port_478",
      "source_port_479",
      "source_port_480",
      "source_port_481",
      "source_port_482"
    ]
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_0",
    "connected_source_port_ids": [
      "source_port_0"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_A1_DROP",
    "display_name": ".U1 > .A1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_1",
    "connected_source_port_ids": [
      "source_port_1"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_A2_DROP",
    "display_name": ".U1 > .A2 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_2",
    "connected_source_port_ids": [
      "source_port_2"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_A4_DROP",
    "display_name": ".U1 > .A4 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_3",
    "connected_source_port_ids": [
      "source_port_3"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_A10_DROP",
    "display_name": ".U1 > .A10 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_4",
    "connected_source_port_ids": [
      "source_port_4"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_A13_DROP",
    "display_name": ".U1 > .A13 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_5",
    "connected_source_port_ids": [
      "source_port_5"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_A16_DROP",
    "display_name": ".U1 > .A16 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_6",
    "connected_source_port_ids": [
      "source_port_6"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_A19_DROP",
    "display_name": ".U1 > .A19 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_7",
    "connected_source_port_ids": [
      "source_port_7"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_A22_DROP",
    "display_name": ".U1 > .A22 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_8",
    "connected_source_port_ids": [
      "source_port_8"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_A23_DROP",
    "display_name": ".U1 > .A23 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_9",
    "connected_source_port_ids": [
      "source_port_9"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_B1_DROP",
    "display_name": ".U1 > .B1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_10",
    "connected_source_port_ids": [
      "source_port_10"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_B5_DROP",
    "display_name": ".U1 > .B5 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_11",
    "connected_source_port_ids": [
      "source_port_11"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_B17_DROP",
    "display_name": ".U1 > .B17 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_12",
    "connected_source_port_ids": [
      "source_port_12"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_B20_DROP",
    "display_name": ".U1 > .B20 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_13",
    "connected_source_port_ids": [
      "source_port_13"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_B23_DROP",
    "display_name": ".U1 > .B23 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_14",
    "connected_source_port_ids": [
      "source_port_14"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_C12_DROP",
    "display_name": ".U1 > .C12 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_15",
    "connected_source_port_ids": [
      "source_port_15"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_C18_DROP",
    "display_name": ".U1 > .C18 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_16",
    "connected_source_port_ids": [
      "source_port_16"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_D1_DROP",
    "display_name": ".U1 > .D1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_17",
    "connected_source_port_ids": [
      "source_port_17"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_E2_DROP",
    "display_name": ".U1 > .E2 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_18",
    "connected_source_port_ids": [
      "source_port_18"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_E6_DROP",
    "display_name": ".U1 > .E6 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_19",
    "connected_source_port_ids": [
      "source_port_19"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_E8_DROP",
    "display_name": ".U1 > .E8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_20",
    "connected_source_port_ids": [
      "source_port_20"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_E9_DROP",
    "display_name": ".U1 > .E9 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_21",
    "connected_source_port_ids": [
      "source_port_21"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_E10_DROP",
    "display_name": ".U1 > .E10 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_22",
    "connected_source_port_ids": [
      "source_port_22"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_E14_DROP",
    "display_name": ".U1 > .E14 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_23",
    "connected_source_port_ids": [
      "source_port_23"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_E15_DROP",
    "display_name": ".U1 > .E15 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_24",
    "connected_source_port_ids": [
      "source_port_24"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_F5_DROP",
    "display_name": ".U1 > .F5 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_25",
    "connected_source_port_ids": [
      "source_port_25"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_F6_DROP",
    "display_name": ".U1 > .F6 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_26",
    "connected_source_port_ids": [
      "source_port_26"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_F18_DROP",
    "display_name": ".U1 > .F18 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_27",
    "connected_source_port_ids": [
      "source_port_27"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_G7_DROP",
    "display_name": ".U1 > .G7 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_28",
    "connected_source_port_ids": [
      "source_port_28"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_G8_DROP",
    "display_name": ".U1 > .G8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_29",
    "connected_source_port_ids": [
      "source_port_29"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_G9_DROP",
    "display_name": ".U1 > .G9 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_30",
    "connected_source_port_ids": [
      "source_port_30"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_G12_DROP",
    "display_name": ".U1 > .G12 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_31",
    "connected_source_port_ids": [
      "source_port_31"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_G15_DROP",
    "display_name": ".U1 > .G15 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_32",
    "connected_source_port_ids": [
      "source_port_32"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_G16_DROP",
    "display_name": ".U1 > .G16 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_33",
    "connected_source_port_ids": [
      "source_port_33"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_G17_DROP",
    "display_name": ".U1 > .G17 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_34",
    "connected_source_port_ids": [
      "source_port_34"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_H1_DROP",
    "display_name": ".U1 > .H1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_35",
    "connected_source_port_ids": [
      "source_port_35"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_H7_DROP",
    "display_name": ".U1 > .H7 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_36",
    "connected_source_port_ids": [
      "source_port_36"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_H14_DROP",
    "display_name": ".U1 > .H14 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_37",
    "connected_source_port_ids": [
      "source_port_37"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_H17_DROP",
    "display_name": ".U1 > .H17 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_38",
    "connected_source_port_ids": [
      "source_port_38"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_K8_DROP",
    "display_name": ".U1 > .K8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_39",
    "connected_source_port_ids": [
      "source_port_39"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_K9_DROP",
    "display_name": ".U1 > .K9 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_40",
    "connected_source_port_ids": [
      "source_port_40"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_K15_DROP",
    "display_name": ".U1 > .K15 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_41",
    "connected_source_port_ids": [
      "source_port_41"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_L7_DROP",
    "display_name": ".U1 > .L7 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_42",
    "connected_source_port_ids": [
      "source_port_42"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_L9_DROP",
    "display_name": ".U1 > .L9 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_43",
    "connected_source_port_ids": [
      "source_port_43"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_L13_DROP",
    "display_name": ".U1 > .L13 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_44",
    "connected_source_port_ids": [
      "source_port_44"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_L16_DROP",
    "display_name": ".U1 > .L16 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_45",
    "connected_source_port_ids": [
      "source_port_45"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_L18_DROP",
    "display_name": ".U1 > .L18 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_46",
    "connected_source_port_ids": [
      "source_port_46"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_M1_DROP",
    "display_name": ".U1 > .M1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_47",
    "connected_source_port_ids": [
      "source_port_47"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_M12_DROP",
    "display_name": ".U1 > .M12 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_48",
    "connected_source_port_ids": [
      "source_port_48"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_N7_DROP",
    "display_name": ".U1 > .N7 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_49",
    "connected_source_port_ids": [
      "source_port_49"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_N9_DROP",
    "display_name": ".U1 > .N9 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_50",
    "connected_source_port_ids": [
      "source_port_50"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_N11_DROP",
    "display_name": ".U1 > .N11 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_51",
    "connected_source_port_ids": [
      "source_port_51"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_N13_DROP",
    "display_name": ".U1 > .N13 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_52",
    "connected_source_port_ids": [
      "source_port_52"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_N16_DROP",
    "display_name": ".U1 > .N16 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_53",
    "connected_source_port_ids": [
      "source_port_53"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_P9_DROP",
    "display_name": ".U1 > .P9 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_54",
    "connected_source_port_ids": [
      "source_port_54"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_P15_DROP",
    "display_name": ".U1 > .P15 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_55",
    "connected_source_port_ids": [
      "source_port_55"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_R1_DROP",
    "display_name": ".U1 > .R1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_56",
    "connected_source_port_ids": [
      "source_port_56"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_R8_DROP",
    "display_name": ".U1 > .R8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_57",
    "connected_source_port_ids": [
      "source_port_57"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_R13_DROP",
    "display_name": ".U1 > .R13 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_58",
    "connected_source_port_ids": [
      "source_port_58"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_R15_DROP",
    "display_name": ".U1 > .R15 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_59",
    "connected_source_port_ids": [
      "source_port_59"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_T2_DROP",
    "display_name": ".U1 > .T2 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_60",
    "connected_source_port_ids": [
      "source_port_60"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_T7_DROP",
    "display_name": ".U1 > .T7 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_61",
    "connected_source_port_ids": [
      "source_port_61"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_T8_DROP",
    "display_name": ".U1 > .T8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_62",
    "connected_source_port_ids": [
      "source_port_62"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_T19_DROP",
    "display_name": ".U1 > .T19 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_63",
    "connected_source_port_ids": [
      "source_port_63"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_U7_DROP",
    "display_name": ".U1 > .U7 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_64",
    "connected_source_port_ids": [
      "source_port_64"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_U8_DROP",
    "display_name": ".U1 > .U8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_65",
    "connected_source_port_ids": [
      "source_port_65"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_U10_DROP",
    "display_name": ".U1 > .U10 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_66",
    "connected_source_port_ids": [
      "source_port_66"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_U13_DROP",
    "display_name": ".U1 > .U13 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_67",
    "connected_source_port_ids": [
      "source_port_67"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_U14_DROP",
    "display_name": ".U1 > .U14 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_68",
    "connected_source_port_ids": [
      "source_port_68"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_U15_DROP",
    "display_name": ".U1 > .U15 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_69",
    "connected_source_port_ids": [
      "source_port_69"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_U17_DROP",
    "display_name": ".U1 > .U17 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_70",
    "connected_source_port_ids": [
      "source_port_70"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_U20_DROP",
    "display_name": ".U1 > .U20 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_71",
    "connected_source_port_ids": [
      "source_port_71"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_V3_DROP",
    "display_name": ".U1 > .V3 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_72",
    "connected_source_port_ids": [
      "source_port_72"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_V18_DROP",
    "display_name": ".U1 > .V18 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_73",
    "connected_source_port_ids": [
      "source_port_73"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_V19_DROP",
    "display_name": ".U1 > .V19 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_74",
    "connected_source_port_ids": [
      "source_port_74"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_W9_DROP",
    "display_name": ".U1 > .W9 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_75",
    "connected_source_port_ids": [
      "source_port_75"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_W10_DROP",
    "display_name": ".U1 > .W10 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_76",
    "connected_source_port_ids": [
      "source_port_76"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_W12_DROP",
    "display_name": ".U1 > .W12 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_77",
    "connected_source_port_ids": [
      "source_port_77"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_W14_DROP",
    "display_name": ".U1 > .W14 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_78",
    "connected_source_port_ids": [
      "source_port_78"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_W15_DROP",
    "display_name": ".U1 > .W15 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_79",
    "connected_source_port_ids": [
      "source_port_79"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_W16_DROP",
    "display_name": ".U1 > .W16 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_80",
    "connected_source_port_ids": [
      "source_port_80"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_W18_DROP",
    "display_name": ".U1 > .W18 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_81",
    "connected_source_port_ids": [
      "source_port_81"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_Y1_DROP",
    "display_name": ".U1 > .Y1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_82",
    "connected_source_port_ids": [
      "source_port_82"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_Y20_DROP",
    "display_name": ".U1 > .Y20 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_83",
    "connected_source_port_ids": [
      "source_port_83"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_Y21_DROP",
    "display_name": ".U1 > .Y21 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_84",
    "connected_source_port_ids": [
      "source_port_84"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AA4_DROP",
    "display_name": ".U1 > .AA4 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_85",
    "connected_source_port_ids": [
      "source_port_85"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AA20_DROP",
    "display_name": ".U1 > .AA20 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_86",
    "connected_source_port_ids": [
      "source_port_86"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AB1_DROP",
    "display_name": ".U1 > .AB1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_87",
    "connected_source_port_ids": [
      "source_port_87"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AB7_DROP",
    "display_name": ".U1 > .AB7 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_88",
    "connected_source_port_ids": [
      "source_port_88"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AB21_DROP",
    "display_name": ".U1 > .AB21 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_89",
    "connected_source_port_ids": [
      "source_port_89"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AB23_DROP",
    "display_name": ".U1 > .AB23 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_90",
    "connected_source_port_ids": [
      "source_port_90"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AC1_DROP",
    "display_name": ".U1 > .AC1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_91",
    "connected_source_port_ids": [
      "source_port_91"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AC2_DROP",
    "display_name": ".U1 > .AC2 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_92",
    "connected_source_port_ids": [
      "source_port_92"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AC11_DROP",
    "display_name": ".U1 > .AC11 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_93",
    "connected_source_port_ids": [
      "source_port_93"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AC14_DROP",
    "display_name": ".U1 > .AC14 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_94",
    "connected_source_port_ids": [
      "source_port_94"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AC19_DROP",
    "display_name": ".U1 > .AC19 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_95",
    "connected_source_port_ids": [
      "source_port_95"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AC22_DROP",
    "display_name": ".U1 > .AC22 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_96",
    "connected_source_port_ids": [
      "source_port_96"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VSS_AC23_DROP",
    "display_name": ".U1 > .AC23 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_97",
    "connected_source_port_ids": [
      "source_port_112"
    ],
    "connected_source_net_ids": [
      "source_net_17"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VDDS_DDR_L8_DROP",
    "display_name": ".U1 > .L8 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_98",
    "connected_source_port_ids": [
      "source_port_113"
    ],
    "connected_source_net_ids": [
      "source_net_17"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VDDS_DDR_M7_DROP",
    "display_name": ".U1 > .M7 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_99",
    "connected_source_port_ids": [
      "source_port_114"
    ],
    "connected_source_net_ids": [
      "source_net_17"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VDDS_DDR_M8_DROP",
    "display_name": ".U1 > .M8 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_100",
    "connected_source_port_ids": [
      "source_port_115"
    ],
    "connected_source_net_ids": [
      "source_net_17"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VDDS_DDR_N8_DROP",
    "display_name": ".U1 > .N8 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_101",
    "connected_source_port_ids": [
      "source_port_116"
    ],
    "connected_source_net_ids": [
      "source_net_17"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_VDDS_DDR_P8_DROP",
    "display_name": ".U1 > .P8 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_102",
    "connected_source_port_ids": [
      "source_port_373"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_A3_DROP",
    "display_name": ".U2 > .A3 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_103",
    "connected_source_port_ids": [
      "source_port_374"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_A10_DROP",
    "display_name": ".U2 > .A10 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_104",
    "connected_source_port_ids": [
      "source_port_375"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_C1_DROP",
    "display_name": ".U2 > .C1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_105",
    "connected_source_port_ids": [
      "source_port_376"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_C5_DROP",
    "display_name": ".U2 > .C5 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_106",
    "connected_source_port_ids": [
      "source_port_377"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_C8_DROP",
    "display_name": ".U2 > .C8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_107",
    "connected_source_port_ids": [
      "source_port_378"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_C12_DROP",
    "display_name": ".U2 > .C12 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_108",
    "connected_source_port_ids": [
      "source_port_379"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_D2_DROP",
    "display_name": ".U2 > .D2 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_109",
    "connected_source_port_ids": [
      "source_port_380"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_D4_DROP",
    "display_name": ".U2 > .D4 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_110",
    "connected_source_port_ids": [
      "source_port_381"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_D9_DROP",
    "display_name": ".U2 > .D9 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_111",
    "connected_source_port_ids": [
      "source_port_382"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_D11_DROP",
    "display_name": ".U2 > .D11 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_112",
    "connected_source_port_ids": [
      "source_port_383"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_E1_DROP",
    "display_name": ".U2 > .E1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_113",
    "connected_source_port_ids": [
      "source_port_384"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_E5_DROP",
    "display_name": ".U2 > .E5 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_114",
    "connected_source_port_ids": [
      "source_port_385"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_E8_DROP",
    "display_name": ".U2 > .E8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_115",
    "connected_source_port_ids": [
      "source_port_386"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_E12_DROP",
    "display_name": ".U2 > .E12 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_116",
    "connected_source_port_ids": [
      "source_port_387"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_G1_DROP",
    "display_name": ".U2 > .G1 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_117",
    "connected_source_port_ids": [
      "source_port_388"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_G3_DROP",
    "display_name": ".U2 > .G3 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_118",
    "connected_source_port_ids": [
      "source_port_389"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_G5_DROP",
    "display_name": ".U2 > .G5 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_119",
    "connected_source_port_ids": [
      "source_port_390"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_G8_DROP",
    "display_name": ".U2 > .G8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_120",
    "connected_source_port_ids": [
      "source_port_391"
    ],
    "connected_source_net_ids": [
      "source_net_16"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
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    "type": "source_trace",
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    "type": "source_trace",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_V5_DROP",
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    "type": "source_trace",
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    "subcircuit_id": "subcircuit_source_group_2",
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  {
    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_W9_DROP",
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    "type": "source_trace",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_W11_DROP",
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    "subcircuit_id": "subcircuit_source_group_2",
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    "subcircuit_id": "subcircuit_source_group_2",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_Y8_DROP",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_AB3_DROP",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_AB5_DROP",
    "display_name": ".U2 > .AB5 to net.GND",
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  {
    "type": "source_trace",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_AB8_DROP",
    "display_name": ".U2 > .AB8 to net.GND",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VSS_AB10_DROP",
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    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_B3_DROP",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_B5_DROP",
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    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_B10_DROP",
    "display_name": ".U2 > .B10 to net.VDD_LPDDR4",
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    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_D1_DROP",
    "display_name": ".U2 > .D1 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    "name": "U2_VDDQ_D5_DROP",
    "display_name": ".U2 > .D5 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "connected_source_port_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_D8_DROP",
    "display_name": ".U2 > .D8 to net.VDD_LPDDR4",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_D12_DROP",
    "display_name": ".U2 > .D12 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_F3_DROP",
    "display_name": ".U2 > .F3 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_F10_DROP",
    "display_name": ".U2 > .F10 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_U3_DROP",
    "display_name": ".U2 > .U3 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_U10_DROP",
    "display_name": ".U2 > .U10 to net.VDD_LPDDR4",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_W1_DROP",
    "display_name": ".U2 > .W1 to net.VDD_LPDDR4",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_W5_DROP",
    "display_name": ".U2 > .W5 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_W8_DROP",
    "display_name": ".U2 > .W8 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "connected_source_port_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_W12_DROP",
    "display_name": ".U2 > .W12 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_AA3_DROP",
    "display_name": ".U2 > .AA3 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_AA5_DROP",
    "display_name": ".U2 > .AA5 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_AA8_DROP",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDDQ_AA10_DROP",
    "display_name": ".U2 > .AA10 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_A4_DROP",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_A9_DROP",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "type": "source_trace",
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_F5_DROP",
    "display_name": ".U2 > .F5 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_F8_DROP",
    "display_name": ".U2 > .F8 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_H1_DROP",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_H5_DROP",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_H8_DROP",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_H12_DROP",
    "display_name": ".U2 > .H12 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_K1_DROP",
    "display_name": ".U2 > .K1 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_K3_DROP",
    "display_name": ".U2 > .K3 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_K10_DROP",
    "display_name": ".U2 > .K10 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_K12_DROP",
    "display_name": ".U2 > .K12 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_N1_DROP",
    "display_name": ".U2 > .N1 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_N3_DROP",
    "display_name": ".U2 > .N3 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_N10_DROP",
    "display_name": ".U2 > .N10 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_N12_DROP",
    "display_name": ".U2 > .N12 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_R1_DROP",
    "display_name": ".U2 > .R1 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_R5_DROP",
    "display_name": ".U2 > .R5 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_R8_DROP",
    "display_name": ".U2 > .R8 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_R12_DROP",
    "display_name": ".U2 > .R12 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_U5_DROP",
    "display_name": ".U2 > .U5 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_U8_DROP",
    "display_name": ".U2 > .U8 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_AB4_DROP",
    "display_name": ".U2 > .AB4 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD2_AB9_DROP",
    "display_name": ".U2 > .AB9 to net.VDD_LPDDR4",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net1"
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  {
    "type": "source_trace",
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    "connected_source_port_ids": [
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    "connected_source_net_ids": [
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    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD1_F1_DROP",
    "display_name": ".U2 > .F1 to net.SOC_DVDD1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
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  {
    "type": "source_trace",
    "source_trace_id": "source_trace_205",
    "connected_source_port_ids": [
      "source_port_476"
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    "connected_source_net_ids": [
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    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD1_F12_DROP",
    "display_name": ".U2 > .F12 to net.SOC_DVDD1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
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  {
    "type": "source_trace",
    "source_trace_id": "source_trace_206",
    "connected_source_port_ids": [
      "source_port_477"
    ],
    "connected_source_net_ids": [
      "source_net_3"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD1_G4_DROP",
    "display_name": ".U2 > .G4 to net.SOC_DVDD1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
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  {
    "type": "source_trace",
    "source_trace_id": "source_trace_207",
    "connected_source_port_ids": [
      "source_port_478"
    ],
    "connected_source_net_ids": [
      "source_net_3"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD1_G9_DROP",
    "display_name": ".U2 > .G9 to net.SOC_DVDD1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
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  {
    "type": "source_trace",
    "source_trace_id": "source_trace_208",
    "connected_source_port_ids": [
      "source_port_479"
    ],
    "connected_source_net_ids": [
      "source_net_3"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U2_VDD1_T4_DROP",
    "display_name": ".U2 > .T4 to net.SOC_DVDD1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net27"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_253",
    "connected_source_port_ids": [
      "source_port_156",
      "source_port_492"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "CK_c",
    "display_name": "U1.DDR0_CK0_n to U2.CK_c",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net28"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_254",
    "connected_source_port_ids": [
      "source_port_157",
      "source_port_493"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "DQS0_t",
    "display_name": "U1.DDR0_DQS0 to U2.DQS0_t",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net29"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_255",
    "connected_source_port_ids": [
      "source_port_158",
      "source_port_494"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "DQS0_c",
    "display_name": "U1.DDR0_DQS0_n to U2.DQS0_c",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net30"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_256",
    "connected_source_port_ids": [
      "source_port_159",
      "source_port_495"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "DQS1_t",
    "display_name": "U1.DDR0_DQS1 to U2.DQS1_t",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net31"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_257",
    "connected_source_port_ids": [
      "source_port_160",
      "source_port_496"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "DQS1_c",
    "display_name": "U1.DDR0_DQS1_n to U2.DQS1_c",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net32"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_258",
    "connected_source_port_ids": [
      "source_port_161",
      "source_port_497"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "RESET_n",
    "display_name": "U1.DDR0_RESET0_n to U2.RESET_n",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net33"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_259",
    "connected_source_port_ids": [
      "source_port_162",
      "source_port_498"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "DMI0",
    "display_name": "U1.DDR0_DM0 to U2.DMI0",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net34"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_260",
    "connected_source_port_ids": [
      "source_port_163",
      "source_port_499"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "DMI1",
    "display_name": "U1.DDR0_DM1 to U2.DMI1",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net35"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_0",
    "message": "Port J9 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_97",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_1",
    "message": "Port J11 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_98",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_2",
    "message": "Port J13 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_99",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_3",
    "message": "Port J15 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_100",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_4",
    "message": "Port K10 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_101",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_5",
    "message": "Port K14 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_102",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_6",
    "message": "Port L15 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_103",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_7",
    "message": "Port M14 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_104",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_8",
    "message": "Port N15 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_105",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_9",
    "message": "Port P10 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_106",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_10",
    "message": "Port P12 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_107",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_11",
    "message": "Port P14 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_108",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_12",
    "message": "Port R9 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_109",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_13",
    "message": "Port R11 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_110",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_14",
    "message": "Port M10 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_111",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_15",
    "message": "Port G14 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_117",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_16",
    "message": "Port T12 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_118",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_17",
    "message": "Port R16 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_119",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_18",
    "message": "Port N17 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_120",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_19",
    "message": "Port L11 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_121",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_20",
    "message": "Port K12 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_122",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_21",
    "message": "Port U12 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_123",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_22",
    "message": "Port J16 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_124",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_23",
    "message": "Port L17 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_125",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_24",
    "message": "Port G10 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_126",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_25",
    "message": "Port H10 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_127",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_26",
    "message": "Port H8 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_128",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_27",
    "message": "Port M17 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_129",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_28",
    "message": "Port T14 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_130",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_29",
    "message": "Port H16 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_131",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_30",
    "message": "Port P16 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_132",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_31",
    "message": "Port U11 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_133",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_32",
    "message": "Port H12 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_134",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_33",
    "message": "Port G13 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_135",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_34",
    "message": "Port N18 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_136",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_35",
    "message": "Port U16 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_137",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_36",
    "message": "Port T10 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_138",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_37",
    "message": "Port T17 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_139",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "source_pin_missing_trace_warning",
    "source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_38",
    "message": "Port T18 on U1 is missing a trace",
    "source_component_id": "source_component_0",
    "source_port_id": "source_port_140",
    "subcircuit_id": "subcircuit_source_group_2",
    "warning_type": "source_pin_missing_trace_warning"
  },
  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_0",
    "center": {
      "x": -9.5,
      "y": 0
    },
    "width": 11.256160000000001,
    "height": 11.25616,
    "layer": "top",
    "rotation": 0,
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "do_not_place": false,
    "obstructs_within_bounds": true,
    "is_allowed_to_be_off_board": false,
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_group",
    "pcb_group_id": "pcb_group_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "SOC_FANOUT",
    "anchor_position": {
      "x": -9.5,
      "y": 0
    },
    "center": {
      "x": -9.5,
      "y": 0
    },
    "width": 17.25616,
    "height": 17.25616,
    "pcb_component_ids": [],
    "source_group_id": "source_group_0",
    "autorouter_configuration": {},
    "anchor_alignment": null,
    "position_mode": "relative_to_group_anchor",
    "positioned_relative_to_pcb_board_id": "pcb_board_0",
    "display_offset_x": -9.5,
    "display_offset_y": 0
  },
  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_1",
    "center": {
      "x": 9.616917,
      "y": 1.81916
    },
    "width": 13.969999999999999,
    "height": 9.120000000000001,
    "layer": "top",
    "rotation": 90,
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "do_not_place": false,
    "obstructs_within_bounds": true,
    "is_allowed_to_be_off_board": false,
    "pcb_group_id": "pcb_group_1"
  },
  {
    "type": "pcb_group",
    "pcb_group_id": "pcb_group_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "DRAM_FANOUT",
    "anchor_position": {
      "x": 9.616917,
      "y": 1.81916
    },
    "center": {
      "x": 9.616917,
      "y": 1.81916
    },
    "width": 19.97,
    "height": 15.120000000000001,
    "pcb_component_ids": [],
    "source_group_id": "source_group_1",
    "autorouter_configuration": {},
    "anchor_alignment": null,
    "position_mode": "relative_to_group_anchor",
    "positioned_relative_to_pcb_board_id": "pcb_board_0",
    "display_offset_x": 9.616917,
    "display_offset_y": 1.81916
  },
  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_2",
    "center": {
      "x": -10.125,
      "y": 0.625
    },
    "width": 1.120000000000001,
    "height": 0.40000000000000013,
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    "obstructs_within_bounds": true,
    "is_allowed_to_be_off_board": false,
    "position_mode": "relative_to_group_anchor",
    "positioned_relative_to_pcb_board_id": "pcb_board_0",
    "display_offset_x": -10.125,
    "display_offset_y": 0.625
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  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_3",
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      "y": -1.75
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    "width": 1.120000000000001,
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    "source_component_id": "source_component_3",
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    "position_mode": "relative_to_group_anchor",
    "positioned_relative_to_pcb_board_id": "pcb_board_0",
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    "display_offset_y": -1.75
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  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_4",
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    "width": 1.120000000000001,
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    "source_component_id": "source_component_4",
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    "obstructs_within_bounds": true,
    "is_allowed_to_be_off_board": false,
    "position_mode": "relative_to_group_anchor",
    "positioned_relative_to_pcb_board_id": "pcb_board_0",
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  },
  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_5",
    "center": {
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      "y": -1.175
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    "width": 1.120000000000001,
    "height": 0.4,
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    "source_component_id": "source_component_5",
    "subcircuit_id": "subcircuit_source_group_2",
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    "obstructs_within_bounds": true,
    "is_allowed_to_be_off_board": false,
    "position_mode": "relative_to_group_anchor",
    "positioned_relative_to_pcb_board_id": "pcb_board_0",
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    "display_offset_y": -1.175
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  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_6",
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      "y": -2.25
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    "width": 0.3999999999999986,
    "height": 1.12,
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    "rotation": 90,
    "source_component_id": "source_component_6",
    "subcircuit_id": "subcircuit_source_group_2",
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    "obstructs_within_bounds": true,
    "is_allowed_to_be_off_board": false,
    "position_mode": "relative_to_group_anchor",
    "positioned_relative_to_pcb_board_id": "pcb_board_0",
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    "display_offset_y": -2.25
  },
  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_7",
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      "y": -2
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    "width": 1.120000000000001,
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    "source_component_id": "source_component_7",
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    "obstructs_within_bounds": true,
    "is_allowed_to_be_off_board": false,
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    "display_offset_y": -2
  },
  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_8",
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    "width": 0.3999999999999986,
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    "source_component_id": "source_component_8",
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    "positioned_relative_to_pcb_board_id": "pcb_board_0",
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  {
    "type": "pcb_component",
    "pcb_component_id": "pcb_component_9",
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      "y": -1.25
    },
    "width": 1.120000000000001,
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    "source_component_id": "source_component_9",
    "subcircuit_id": "subcircuit_source_group_2",
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    "is_allowed_to_be_off_board": false,
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    "positioned_relative_to_pcb_board_id": "pcb_board_0",
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    "display_offset_y": -1.25
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  {
    "type": "pcb_board",
    "pcb_board_id": "pcb_board_0",
    "source_board_id": "source_board_0",
    "center": {
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      "y": 0
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    "thickness": 1.4,
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    "width": 40,
    "height": 20,
    "material": "fr4",
    "is_via_in_pad_allowed": false,
    "allow_blind_and_buried_vias": false,
    "min_trace_width": 0.08128,
    "min_via_hole_diameter": 0.15,
    "min_via_pad_diameter": 0.24,
    "min_via_hole_edge_to_via_hole_edge_clearance": 0.1016,
    "min_via_edge_to_pad_edge_clearance": 0.08128,
    "min_trace_to_pad_edge_clearance": 0.05,
    "min_pad_edge_to_pad_edge_clearance": 0.1,
    "min_plated_hole_drill_edge_to_drill_edge_clearance": 0.15,
    "min_board_edge_clearance": 0.2
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  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_0",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_0",
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    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A1"
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    "is_covered_with_solder_mask": false,
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    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_0",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_1",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_1",
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    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A2"
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    "is_covered_with_solder_mask": false,
    "x": -14.5,
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    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "x": -14.5,
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    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_1",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_2",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_180",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A3"
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    "is_covered_with_solder_mask": false,
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  },
  {
    "type": "pcb_solder_paste",
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    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_2",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_3",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_2",
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    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A4"
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    "is_covered_with_solder_mask": false,
    "x": -13.5,
    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_3",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_4",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_181",
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    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A5"
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    "is_covered_with_solder_mask": false,
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    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_5",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_182",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A6"
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    "is_covered_with_solder_mask": false,
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    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_5",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_6",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_183",
    "layer": "top",
    "shape": "circle",
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    "port_hints": [
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      "A7"
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    "is_covered_with_solder_mask": false,
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    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "layer": "top",
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    "x": -12,
    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_6",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_7",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_184",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A8"
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    "is_covered_with_solder_mask": false,
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    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "x": -11.5,
    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_7",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_8",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_185",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A9"
    ],
    "is_covered_with_solder_mask": false,
    "x": -11,
    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_8",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_9",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_3",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A10"
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    "is_covered_with_solder_mask": false,
    "x": -10.5,
    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "x": -10.5,
    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_9",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_10",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_186",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A11"
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    "is_covered_with_solder_mask": false,
    "x": -10,
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    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "pcb_solder_paste",
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    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_10",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_11",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_187",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A12"
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    "is_covered_with_solder_mask": false,
    "x": -9.5,
    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "pcb_solder_paste",
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    "x": -9.5,
    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_11",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_12",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_4",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A13"
    ],
    "is_covered_with_solder_mask": false,
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    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "pcb_solder_paste",
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    "radius": 0.089656,
    "x": -9,
    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_12",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_13",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_188",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A14"
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    "is_covered_with_solder_mask": false,
    "x": -8.5,
    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "pcb_solder_paste",
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    "layer": "top",
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    "x": -8.5,
    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_13",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_14",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_189",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A15"
    ],
    "is_covered_with_solder_mask": false,
    "x": -8,
    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "layer": "top",
    "shape": "circle",
    "radius": 0.089656,
    "x": -8,
    "y": 5.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_14",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_15",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_5",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "A16"
    ],
    "is_covered_with_solder_mask": false,
    "x": -7.5,
    "y": 5.5,
    "subcircuit_id": "subcircuit_source_group_2"
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  {
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    "pcb_group_id": "pcb_group_0"
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  {
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  {
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  {
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  {
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  {
    "type": "pcb_smtpad",
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      "B14"
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    "is_covered_with_solder_mask": false,
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  {
    "type": "pcb_solder_paste",
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    "pcb_component_id": "pcb_component_0",
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  {
    "type": "pcb_smtpad",
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    "port_hints": [
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      "B15"
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    "is_covered_with_solder_mask": false,
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  {
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    "pcb_smtpad_id": "pcb_smtpad_37",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
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    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_207",
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      "B16"
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  },
  {
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    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
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    "port_hints": [
      "pin40",
      "B17"
    ],
    "is_covered_with_solder_mask": false,
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  },
  {
    "type": "pcb_solder_paste",
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    "pcb_smtpad_id": "pcb_smtpad_39",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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    "pcb_port_id": "pcb_port_208",
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    "port_hints": [
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      "B18"
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  {
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    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_209",
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      "B19"
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    "is_covered_with_solder_mask": false,
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  {
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    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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      "B20"
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    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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      "B21"
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  {
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    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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      "B22"
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  {
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  {
    "type": "pcb_smtpad",
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      "B23"
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  {
    "type": "pcb_solder_paste",
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    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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    "pcb_component_id": "pcb_component_0",
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      "C1"
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    "is_covered_with_solder_mask": false,
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  {
    "type": "pcb_solder_paste",
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    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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    "pcb_component_id": "pcb_component_0",
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    "port_hints": [
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      "C2"
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  {
    "type": "pcb_solder_paste",
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    "subcircuit_id": "subcircuit_source_group_2",
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    "type": "pcb_smtpad",
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    "port_hints": [
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  {
    "type": "pcb_solder_paste",
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    "pcb_group_id": "pcb_group_0"
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    "type": "pcb_smtpad",
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    "type": "pcb_solder_paste",
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  {
    "type": "pcb_smtpad",
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  {
    "type": "pcb_solder_paste",
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    "subcircuit_id": "subcircuit_source_group_2",
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  {
    "type": "pcb_smtpad",
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      "C11"
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    "is_covered_with_solder_mask": false,
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  {
    "type": "pcb_solder_paste",
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    "type": "pcb_smtpad",
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  {
    "type": "pcb_solder_paste",
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    "subcircuit_id": "subcircuit_source_group_2",
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  {
    "type": "pcb_smtpad",
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      "C13"
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    "is_covered_with_solder_mask": false,
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  {
    "type": "pcb_solder_paste",
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    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_53",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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  {
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    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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    "port_hints": [
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      "C18"
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  {
    "type": "pcb_solder_paste",
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    "subcircuit_id": "subcircuit_source_group_2",
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  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_56",
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    "port_hints": [
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      "C20"
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  {
    "type": "pcb_solder_paste",
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    "pcb_component_id": "pcb_component_0",
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    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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    "pcb_component_id": "pcb_component_0",
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    "port_hints": [
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      "C22"
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    "is_covered_with_solder_mask": false,
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    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "pcb_solder_paste",
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    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_57",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_58",
    "pcb_component_id": "pcb_component_0",
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    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "C23"
    ],
    "is_covered_with_solder_mask": false,
    "x": -4,
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    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "pcb_solder_paste",
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    "layer": "top",
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    "y": 4.5,
    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_58",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
  },
  {
    "type": "pcb_smtpad",
    "pcb_smtpad_id": "pcb_smtpad_59",
    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_16",
    "layer": "top",
    "shape": "circle",
    "radius": 0.12808,
    "port_hints": [
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      "D1"
    ],
    "is_covered_with_solder_mask": false,
    "x": -15,
    "y": 4,
    "subcircuit_id": "subcircuit_source_group_2"
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    "type": "pcb_smtpad",
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  {
    "type": "pcb_smtpad",
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      "E11"
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    "pcb_group_id": "pcb_group_0"
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  {
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      "E12"
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  {
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    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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      "E13"
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  {
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    "pcb_group_id": "pcb_group_0"
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    "type": "pcb_smtpad",
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  {
    "type": "pcb_smtpad",
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    "type": "pcb_smtpad",
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    "type": "pcb_smtpad",
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    "type": "pcb_smtpad",
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    "type": "pcb_solder_paste",
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    "type": "pcb_smtpad",
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    "type": "pcb_smtpad",
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    "type": "pcb_smtpad",
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    "port_hints": [
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  {
    "type": "pcb_smtpad",
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    "port_hints": [
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      "F21"
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  {
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  {
    "type": "pcb_smtpad",
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    "port_hints": [
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      "F22"
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  {
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  {
    "type": "pcb_smtpad",
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    "port_hints": [
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      "F23"
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  {
    "type": "pcb_solder_paste",
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    "pcb_component_id": "pcb_component_0",
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    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_157",
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    "shape": "circle",
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    "port_hints": [
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      "G1"
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    "is_covered_with_solder_mask": false,
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  {
    "type": "pcb_solder_paste",
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    "pcb_component_id": "pcb_component_0",
    "pcb_smtpad_id": "pcb_smtpad_102",
    "subcircuit_id": "subcircuit_source_group_2",
    "pcb_group_id": "pcb_group_0"
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  {
    "type": "pcb_smtpad",
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    "pcb_component_id": "pcb_component_0",
    "pcb_port_id": "pcb_port_158",
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    "port_hints": [
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      "G2"
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    "is_covered_with_solder_mask": false,
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    "subcircuit_id": "subcircuit_source_group_2"
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  {
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    "type": "pcb_smtpad",
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  {
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    "pcb_component_id": "pcb_component_0",
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    "subcircuit_id": "subcircuit_source_group_2",
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  {
    "type": "pcb_smtpad",
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    "port_hints": [
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      "H6"
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    "is_covered_with_solder_mask": false,
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  {
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    "pcb_component_id": "pcb_component_0",
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    "subcircuit_id": "subcircuit_source_group_2",
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  {
    "type": "pcb_smtpad",
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    "port_hints": [
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      "H7"
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    "is_covered_with_solder_mask": false,
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    "subcircuit_id": "subcircuit_source_group_2"
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    "pcb_group_id": "pcb_group_0"
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  {
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  {
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  {
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  {
    "type": "pcb_smtpad",
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  {
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    "type": "pcb_trace",
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      "fanout-exit:source_trace_26:source-0"
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    "pcb_copper_pour_id": "pcb_copper_pour_17",
    "shape": "brep",
    "layer": "inner3",
    "brep_shape": {
      "outer_ring": {
        "vertices": [
          {
            "x": -13.5,
            "y": 2.447364
          },
          {
            "x": -13.523726,
            "y": 2.476274
          },
          {
            "x": -13.552636,
            "y": 2.5
          },
          {
            "x": -13.523726,
            "y": 2.523726
          },
          {
            "x": -13.5,
            "y": 2.552636
          },
          {
            "x": -13.476274,
            "y": 2.523726
          },
          {
            "x": -13.447364,
            "y": 2.5
          },
          {
            "x": -13.476274,
            "y": 2.476274
          }
        ]
      },
      "inner_rings": []
    },
    "source_net_id": "source_net_3",
    "subcircuit_id": "subcircuit_source_group_2",
    "covered_with_solder_mask": true
  },
  {
    "type": "pcb_copper_pour",
    "pcb_copper_pour_id": "pcb_copper_pour_18",
    "shape": "brep",
    "layer": "inner3",
    "brep_shape": {
      "outer_ring": {
        "vertices": [
          {
            "x": -14,
            "y": 2.447364
          },
          {
            "x": -14.023726,
            "y": 2.476274
          },
          {
            "x": -14.052636,
            "y": 2.5
          },
          {
            "x": -14.023726,
            "y": 2.523726
          },
          {
            "x": -14,
            "y": 2.552636
          },
          {
            "x": -13.976274,
            "y": 2.523726
          },
          {
            "x": -13.947364,
            "y": 2.5
          },
          {
            "x": -13.976274,
            "y": 2.476274
          }
        ]
      },
      "inner_rings": []
    },
    "source_net_id": "source_net_3",
    "subcircuit_id": "subcircuit_source_group_2",
    "covered_with_solder_mask": true
  },
  {
    "type": "pcb_copper_pour",
    "pcb_copper_pour_id": "pcb_copper_pour_19",
    "shape": "brep",
    "layer": "inner3",
    "brep_shape": {
      "outer_ring": {
        "vertices": [
          {
            "x": -14.5,
            "y": 2.447364
          },
          {
            "x": -14.523726,
            "y": 2.476274
          },
          {
            "x": -14.552636,
            "y": 2.5
          },
          {
            "x": -14.523726,
            "y": 2.523726
          },
          {
            "x": -14.5,
            "y": 2.552636
          },
          {
            "x": -14.476274,
            "y": 2.523726
          },
          {
            "x": -14.447364,
            "y": 2.5
          },
          {
            "x": -14.476274,
            "y": 2.476274
          }
        ]
      },
      "inner_rings": []
    },
    "source_net_id": "source_net_3",
    "subcircuit_id": "subcircuit_source_group_2",
    "covered_with_solder_mask": true
  },
  {
    "type": "pcb_copper_pour",
    "pcb_copper_pour_id": "pcb_copper_pour_20",
    "shape": "brep",
    "layer": "inner3",
    "brep_shape": {
      "outer_ring": {
        "vertices": [
          {
            "x": -13.5,
            "y": 2.947364
          },
          {
            "x": -13.523726,
            "y": 2.976274
          },
          {
            "x": -13.552636,
            "y": 3
          },
          {
            "x": -13.523726,
            "y": 3.023726
          },
          {
            "x": -13.5,
            "y": 3.052636
          },
          {
            "x": -13.476274,
            "y": 3.023726
          },
          {
            "x": -13.447364,
            "y": 3
          },
          {
            "x": -13.476274,
            "y": 2.976274
          }
        ]
      },
      "inner_rings": []
    },
    "source_net_id": "source_net_3",
    "subcircuit_id": "subcircuit_source_group_2",
    "covered_with_solder_mask": true
  },
  {
    "type": "pcb_copper_pour",
    "pcb_copper_pour_id": "pcb_copper_pour_21",
    "shape": "brep",
    "layer": "inner3",
    "brep_shape": {
      "outer_ring": {
        "vertices": [
          {
            "x": -15,
            "y": 2.947364
          },
          {
            "x": -15.023726,
            "y": 2.976274
          },
          {
            "x": -15.052636,
            "y": 3
          },
          {
            "x": -15.023726,
            "y": 3.023726
          },
          {
            "x": -15,
            "y": 3.052636
          },
          {
            "x": -14.976274,
            "y": 3.023726
          },
          {
            "x": -14.947364,
            "y": 3
          },
          {
            "x": -14.976274,
            "y": 2.976274
          }
        ]
      },
      "inner_rings": []
    },
    "source_net_id": "source_net_3",
    "subcircuit_id": "subcircuit_source_group_2",
    "covered_with_solder_mask": true
  },
  {
    "type": "pcb_copper_pour",
    "pcb_copper_pour_id": "pcb_copper_pour_22",
    "shape": "brep",
    "layer": "inner3",
    "brep_shape": {
      "outer_ring": {
        "vertices": [
          {
            "x": -15,
            "y": 3.447364
          },
          {
            "x": -15.023726,
            "y": 3.476274
          },
          {
            "x": -15.052636,
            "y": 3.5
          },
          {
            "x": -15.023726,
            "y": 3.523726
          },
          {
            "x": -15,
            "y": 3.552636
          },
          {
            "x": -14.976274,
            "y": 3.523726
          },
          {
            "x": -14.947364,
            "y": 3.5
          },
          {
            "x": -14.976274,
            "y": 3.476274
          }
        ]
      },
      "inner_rings": []
    },
    "source_net_id": "source_net_3",
    "subcircuit_id": "subcircuit_source_group_2",
    "covered_with_solder_mask": true
  },
  {
    "type": "source_component_pins_underspecified_warning",
    "source_component_pins_underspecified_warning_id": "source_component_pins_underspecified_warning_0",
    "warning_type": "source_component_pins_underspecified_warning",
    "message": "All pins on U2 are underspecified (no pinAttributes set)",
    "source_component_id": "source_component_1",
    "source_port_ids": [
      "source_port_373",
      "source_port_374",
      "source_port_375",
      "source_port_376",
      "source_port_377",
      "source_port_378",
      "source_port_379",
      "source_port_380",
      "source_port_381",
      "source_port_382",
      "source_port_383",
      "source_port_384",
      "source_port_385",
      "source_port_386",
      "source_port_387",
      "source_port_388",
      "source_port_389",
      "source_port_390",
      "source_port_391",
      "source_port_392",
      "source_port_393",
      "source_port_394",
      "source_port_395",
      "source_port_396",
      "source_port_397",
      "source_port_398",
      "source_port_399",
      "source_port_400",
      "source_port_401",
      "source_port_402",
      "source_port_403",
      "source_port_404",
      "source_port_405",
      "source_port_406",
      "source_port_407",
      "source_port_408",
      "source_port_409",
      "source_port_410",
      "source_port_411",
      "source_port_412",
      "source_port_413",
      "source_port_414",
      "source_port_415",
      "source_port_416",
      "source_port_417",
      "source_port_418",
      "source_port_419",
      "source_port_420",
      "source_port_421",
      "source_port_422",
      "source_port_423",
      "source_port_424",
      "source_port_425",
      "source_port_426",
      "source_port_427",
      "source_port_428",
      "source_port_429",
      "source_port_430",
      "source_port_431",
      "source_port_432",
      "source_port_433",
      "source_port_434",
      "source_port_435",
      "source_port_436",
      "source_port_437",
      "source_port_438",
      "source_port_439",
      "source_port_440",
      "source_port_441",
      "source_port_442",
      "source_port_443",
      "source_port_444",
      "source_port_445",
      "source_port_446",
      "source_port_447",
      "source_port_448",
      "source_port_449",
      "source_port_450",
      "source_port_451",
      "source_port_452",
      "source_port_453",
      "source_port_454",
      "source_port_455",
      "source_port_456",
      "source_port_457",
      "source_port_458",
      "source_port_459",
      "source_port_460",
      "source_port_461",
      "source_port_462",
      "source_port_463",
      "source_port_464",
      "source_port_465",
      "source_port_466",
      "source_port_467",
      "source_port_468",
      "source_port_469",
      "source_port_470",
      "source_port_471",
      "source_port_472",
      "source_port_473",
      "source_port_474",
      "source_port_475",
      "source_port_476",
      "source_port_477",
      "source_port_478",
      "source_port_479",
      "source_port_480",
      "source_port_481",
      "source_port_482",
      "source_port_483",
      "source_port_484",
      "source_port_485",
      "source_port_486",
      "source_port_487",
      "source_port_488",
      "source_port_489",
      "source_port_490",
      "source_port_491",
      "source_port_492",
      "source_port_493",
      "source_port_494",
      "source_port_495",
      "source_port_496",
      "source_port_497",
      "source_port_498",
      "source_port_499",
      "source_port_500",
      "source_port_501",
      "source_port_502",
      "source_port_503",
      "source_port_504",
      "source_port_505",
      "source_port_506",
      "source_port_507",
      "source_port_508",
      "source_port_509",
      "source_port_510",
      "source_port_511",
      "source_port_512",
      "source_port_513",
      "source_port_514",
      "source_port_515",
      "source_port_516",
      "source_port_517",
      "source_port_518",
      "source_port_519",
      "source_port_520",
      "source_port_521",
      "source_port_522",
      "source_port_523",
      "source_port_524",
      "source_port_525",
      "source_port_526",
      "source_port_527",
      "source_port_528",
      "source_port_529",
      "source_port_530",
      "source_port_531",
      "source_port_532",
      "source_port_533",
      "source_port_534",
      "source_port_535",
      "source_port_536",
      "source_port_537",
      "source_port_538",
      "source_port_539",
      "source_port_540",
      "source_port_541",
      "source_port_542",
      "source_port_543",
      "source_port_544",
      "source_port_545",
      "source_port_546",
      "source_port_547",
      "source_port_548",
      "source_port_549",
      "source_port_550",
      "source_port_551",
      "source_port_552",
      "source_port_553",
      "source_port_554",
      "source_port_555",
      "source_port_556",
      "source_port_557",
      "source_port_558",
      "source_port_559",
      "source_port_560",
      "source_port_561",
      "source_port_562",
      "source_port_563",
      "source_port_564",
      "source_port_565",
      "source_port_566",
      "source_port_567",
      "source_port_568",
      "source_port_569",
      "source_port_570",
      "source_port_571",
      "source_port_572"
    ],
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_no_power_pin_defined_warning",
    "source_no_power_pin_defined_warning_id": "source_no_power_pin_defined_warning_0",
    "warning_type": "source_no_power_pin_defined_warning",
    "message": "U2 has no pin with requires_power=true",
    "source_component_id": "source_component_1",
    "source_port_ids": [
      "source_port_373",
      "source_port_374",
      "source_port_375",
      "source_port_376",
      "source_port_377",
      "source_port_378",
      "source_port_379",
      "source_port_380",
      "source_port_381",
      "source_port_382",
      "source_port_383",
      "source_port_384",
      "source_port_385",
      "source_port_386",
      "source_port_387",
      "source_port_388",
      "source_port_389",
      "source_port_390",
      "source_port_391",
      "source_port_392",
      "source_port_393",
      "source_port_394",
      "source_port_395",
      "source_port_396",
      "source_port_397",
      "source_port_398",
      "source_port_399",
      "source_port_400",
      "source_port_401",
      "source_port_402",
      "source_port_403",
      "source_port_404",
      "source_port_405",
      "source_port_406",
      "source_port_407",
      "source_port_408",
      "source_port_409",
      "source_port_410",
      "source_port_411",
      "source_port_412",
      "source_port_413",
      "source_port_414",
      "source_port_415",
      "source_port_416",
      "source_port_417",
      "source_port_418",
      "source_port_419",
      "source_port_420",
      "source_port_421",
      "source_port_422",
      "source_port_423",
      "source_port_424",
      "source_port_425",
      "source_port_426",
      "source_port_427",
      "source_port_428",
      "source_port_429",
      "source_port_430",
      "source_port_431",
      "source_port_432",
      "source_port_433",
      "source_port_434",
      "source_port_435",
      "source_port_436",
      "source_port_437",
      "source_port_438",
      "source_port_439",
      "source_port_440",
      "source_port_441",
      "source_port_442",
      "source_port_443",
      "source_port_444",
      "source_port_445",
      "source_port_446",
      "source_port_447",
      "source_port_448",
      "source_port_449",
      "source_port_450",
      "source_port_451",
      "source_port_452",
      "source_port_453",
      "source_port_454",
      "source_port_455",
      "source_port_456",
      "source_port_457",
      "source_port_458",
      "source_port_459",
      "source_port_460",
      "source_port_461",
      "source_port_462",
      "source_port_463",
      "source_port_464",
      "source_port_465",
      "source_port_466",
      "source_port_467",
      "source_port_468",
      "source_port_469",
      "source_port_470",
      "source_port_471",
      "source_port_472",
      "source_port_473",
      "source_port_474",
      "source_port_475",
      "source_port_476",
      "source_port_477",
      "source_port_478",
      "source_port_479",
      "source_port_480",
      "source_port_481",
      "source_port_482",
      "source_port_483",
      "source_port_484",
      "source_port_485",
      "source_port_486",
      "source_port_487",
      "source_port_488",
      "source_port_489",
      "source_port_490",
      "source_port_491",
      "source_port_492",
      "source_port_493",
      "source_port_494",
      "source_port_495",
      "source_port_496",
      "source_port_497",
      "source_port_498",
      "source_port_499",
      "source_port_500",
      "source_port_501",
      "source_port_502",
      "source_port_503",
      "source_port_504",
      "source_port_505",
      "source_port_506",
      "source_port_507",
      "source_port_508",
      "source_port_509",
      "source_port_510",
      "source_port_511",
      "source_port_512",
      "source_port_513",
      "source_port_514",
      "source_port_515",
      "source_port_516",
      "source_port_517",
      "source_port_518",
      "source_port_519",
      "source_port_520",
      "source_port_521",
      "source_port_522",
      "source_port_523",
      "source_port_524",
      "source_port_525",
      "source_port_526",
      "source_port_527",
      "source_port_528",
      "source_port_529",
      "source_port_530",
      "source_port_531",
      "source_port_532",
      "source_port_533",
      "source_port_534",
      "source_port_535",
      "source_port_536",
      "source_port_537",
      "source_port_538",
      "source_port_539",
      "source_port_540",
      "source_port_541",
      "source_port_542",
      "source_port_543",
      "source_port_544",
      "source_port_545",
      "source_port_546",
      "source_port_547",
      "source_port_548",
      "source_port_549",
      "source_port_550",
      "source_port_551",
      "source_port_552",
      "source_port_553",
      "source_port_554",
      "source_port_555",
      "source_port_556",
      "source_port_557",
      "source_port_558",
      "source_port_559",
      "source_port_560",
      "source_port_561",
      "source_port_562",
      "source_port_563",
      "source_port_564",
      "source_port_565",
      "source_port_566",
      "source_port_567",
      "source_port_568",
      "source_port_569",
      "source_port_570",
      "source_port_571",
      "source_port_572"
    ],
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_no_ground_pin_defined_warning",
    "source_no_ground_pin_defined_warning_id": "source_no_ground_pin_defined_warning_0",
    "warning_type": "source_no_ground_pin_defined_warning",
    "message": "U1 has no pin with requires_ground=true",
    "source_component_id": "source_component_0",
    "source_port_ids": [
      "source_port_0",
      "source_port_1",
      "source_port_2",
      "source_port_3",
      "source_port_4",
      "source_port_5",
      "source_port_6",
      "source_port_7",
      "source_port_8",
      "source_port_9",
      "source_port_10",
      "source_port_11",
      "source_port_12",
      "source_port_13",
      "source_port_14",
      "source_port_15",
      "source_port_16",
      "source_port_17",
      "source_port_18",
      "source_port_19",
      "source_port_20",
      "source_port_21",
      "source_port_22",
      "source_port_23",
      "source_port_24",
      "source_port_25",
      "source_port_26",
      "source_port_27",
      "source_port_28",
      "source_port_29",
      "source_port_30",
      "source_port_31",
      "source_port_32",
      "source_port_33",
      "source_port_34",
      "source_port_35",
      "source_port_36",
      "source_port_37",
      "source_port_38",
      "source_port_39",
      "source_port_40",
      "source_port_41",
      "source_port_42",
      "source_port_43",
      "source_port_44",
      "source_port_45",
      "source_port_46",
      "source_port_47",
      "source_port_48",
      "source_port_49",
      "source_port_50",
      "source_port_51",
      "source_port_52",
      "source_port_53",
      "source_port_54",
      "source_port_55",
      "source_port_56",
      "source_port_57",
      "source_port_58",
      "source_port_59",
      "source_port_60",
      "source_port_61",
      "source_port_62",
      "source_port_63",
      "source_port_64",
      "source_port_65",
      "source_port_66",
      "source_port_67",
      "source_port_68",
      "source_port_69",
      "source_port_70",
      "source_port_71",
      "source_port_72",
      "source_port_73",
      "source_port_74",
      "source_port_75",
      "source_port_76",
      "source_port_77",
      "source_port_78",
      "source_port_79",
      "source_port_80",
      "source_port_81",
      "source_port_82",
      "source_port_83",
      "source_port_84",
      "source_port_85",
      "source_port_86",
      "source_port_87",
      "source_port_88",
      "source_port_89",
      "source_port_90",
      "source_port_91",
      "source_port_92",
      "source_port_93",
      "source_port_94",
      "source_port_95",
      "source_port_96",
      "source_port_97",
      "source_port_98",
      "source_port_99",
      "source_port_100",
      "source_port_101",
      "source_port_102",
      "source_port_103",
      "source_port_104",
      "source_port_105",
      "source_port_106",
      "source_port_107",
      "source_port_108",
      "source_port_109",
      "source_port_110",
      "source_port_111",
      "source_port_112",
      "source_port_113",
      "source_port_114",
      "source_port_115",
      "source_port_116",
      "source_port_117",
      "source_port_118",
      "source_port_119",
      "source_port_120",
      "source_port_121",
      "source_port_122",
      "source_port_123",
      "source_port_124",
      "source_port_125",
      "source_port_126",
      "source_port_127",
      "source_port_128",
      "source_port_129",
      "source_port_130",
      "source_port_131",
      "source_port_132",
      "source_port_133",
      "source_port_134",
      "source_port_135",
      "source_port_136",
      "source_port_137",
      "source_port_138",
      "source_port_139",
      "source_port_140",
      "source_port_141",
      "source_port_142",
      "source_port_143",
      "source_port_144",
      "source_port_145",
      "source_port_146",
      "source_port_147",
      "source_port_148",
      "source_port_149",
      "source_port_150",
      "source_port_151",
      "source_port_152",
      "source_port_153",
      "source_port_154",
      "source_port_155",
      "source_port_156",
      "source_port_157",
      "source_port_158",
      "source_port_159",
      "source_port_160",
      "source_port_161",
      "source_port_162",
      "source_port_163",
      "source_port_164",
      "source_port_165",
      "source_port_166",
      "source_port_167",
      "source_port_168",
      "source_port_169",
      "source_port_170",
      "source_port_171",
      "source_port_172",
      "source_port_173",
      "source_port_174",
      "source_port_175",
      "source_port_176",
      "source_port_177",
      "source_port_178",
      "source_port_179",
      "source_port_180",
      "source_port_181",
      "source_port_182",
      "source_port_183",
      "source_port_184",
      "source_port_185",
      "source_port_186",
      "source_port_187",
      "source_port_188",
      "source_port_189",
      "source_port_190",
      "source_port_191",
      "source_port_192",
      "source_port_193",
      "source_port_194",
      "source_port_195",
      "source_port_196",
      "source_port_197",
      "source_port_198",
      "source_port_199",
      "source_port_200",
      "source_port_201",
      "source_port_202",
      "source_port_203",
      "source_port_204",
      "source_port_205",
      "source_port_206",
      "source_port_207",
      "source_port_208",
      "source_port_209",
      "source_port_210",
      "source_port_211",
      "source_port_212",
      "source_port_213",
      "source_port_214",
      "source_port_215",
      "source_port_216",
      "source_port_217",
      "source_port_218",
      "source_port_219",
      "source_port_220",
      "source_port_221",
      "source_port_222",
      "source_port_223",
      "source_port_224",
      "source_port_225",
      "source_port_226",
      "source_port_227",
      "source_port_228",
      "source_port_229",
      "source_port_230",
      "source_port_231",
      "source_port_232",
      "source_port_233",
      "source_port_234",
      "source_port_235",
      "source_port_236",
      "source_port_237",
      "source_port_238",
      "source_port_239",
      "source_port_240",
      "source_port_241",
      "source_port_242",
      "source_port_243",
      "source_port_244",
      "source_port_245",
      "source_port_246",
      "source_port_247",
      "source_port_248",
      "source_port_249",
      "source_port_250",
      "source_port_251",
      "source_port_252",
      "source_port_253",
      "source_port_254",
      "source_port_255",
      "source_port_256",
      "source_port_257",
      "source_port_258",
      "source_port_259",
      "source_port_260",
      "source_port_261",
      "source_port_262",
      "source_port_263",
      "source_port_264",
      "source_port_265",
      "source_port_266",
      "source_port_267",
      "source_port_268",
      "source_port_269",
      "source_port_270",
      "source_port_271",
      "source_port_272",
      "source_port_273",
      "source_port_274",
      "source_port_275",
      "source_port_276",
      "source_port_277",
      "source_port_278",
      "source_port_279",
      "source_port_280",
      "source_port_281",
      "source_port_282",
      "source_port_283",
      "source_port_284",
      "source_port_285",
      "source_port_286",
      "source_port_287",
      "source_port_288",
      "source_port_289",
      "source_port_290",
      "source_port_291",
      "source_port_292",
      "source_port_293",
      "source_port_294",
      "source_port_295",
      "source_port_296",
      "source_port_297",
      "source_port_298",
      "source_port_299",
      "source_port_300",
      "source_port_301",
      "source_port_302",
      "source_port_303",
      "source_port_304",
      "source_port_305",
      "source_port_306",
      "source_port_307",
      "source_port_308",
      "source_port_309",
      "source_port_310",
      "source_port_311",
      "source_port_312",
      "source_port_313",
      "source_port_314",
      "source_port_315",
      "source_port_316",
      "source_port_317",
      "source_port_318",
      "source_port_319",
      "source_port_320",
      "source_port_321",
      "source_port_322",
      "source_port_323",
      "source_port_324",
      "source_port_325",
      "source_port_326",
      "source_port_327",
      "source_port_328",
      "source_port_329",
      "source_port_330",
      "source_port_331",
      "source_port_332",
      "source_port_333",
      "source_port_334",
      "source_port_335",
      "source_port_336",
      "source_port_337",
      "source_port_338",
      "source_port_339",
      "source_port_340",
      "source_port_341",
      "source_port_342",
      "source_port_343",
      "source_port_344",
      "source_port_345",
      "source_port_346",
      "source_port_347",
      "source_port_348",
      "source_port_349",
      "source_port_350",
      "source_port_351",
      "source_port_352",
      "source_port_353",
      "source_port_354",
      "source_port_355",
      "source_port_356",
      "source_port_357",
      "source_port_358",
      "source_port_359",
      "source_port_360",
      "source_port_361",
      "source_port_362",
      "source_port_363",
      "source_port_364",
      "source_port_365",
      "source_port_366",
      "source_port_367",
      "source_port_368",
      "source_port_369",
      "source_port_370",
      "source_port_371",
      "source_port_372"
    ],
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_no_ground_pin_defined_warning",
    "source_no_ground_pin_defined_warning_id": "source_no_ground_pin_defined_warning_1",
    "warning_type": "source_no_ground_pin_defined_warning",
    "message": "U2 has no pin with requires_ground=true",
    "source_component_id": "source_component_1",
    "source_port_ids": [
      "source_port_373",
      "source_port_374",
      "source_port_375",
      "source_port_376",
      "source_port_377",
      "source_port_378",
      "source_port_379",
      "source_port_380",
      "source_port_381",
      "source_port_382",
      "source_port_383",
      "source_port_384",
      "source_port_385",
      "source_port_386",
      "source_port_387",
      "source_port_388",
      "source_port_389",
      "source_port_390",
      "source_port_391",
      "source_port_392",
      "source_port_393",
      "source_port_394",
      "source_port_395",
      "source_port_396",
      "source_port_397",
      "source_port_398",
      "source_port_399",
      "source_port_400",
      "source_port_401",
      "source_port_402",
      "source_port_403",
      "source_port_404",
      "source_port_405",
      "source_port_406",
      "source_port_407",
      "source_port_408",
      "source_port_409",
      "source_port_410",
      "source_port_411",
      "source_port_412",
      "source_port_413",
      "source_port_414",
      "source_port_415",
      "source_port_416",
      "source_port_417",
      "source_port_418",
      "source_port_419",
      "source_port_420",
      "source_port_421",
      "source_port_422",
      "source_port_423",
      "source_port_424",
      "source_port_425",
      "source_port_426",
      "source_port_427",
      "source_port_428",
      "source_port_429",
      "source_port_430",
      "source_port_431",
      "source_port_432",
      "source_port_433",
      "source_port_434",
      "source_port_435",
      "source_port_436",
      "source_port_437",
      "source_port_438",
      "source_port_439",
      "source_port_440",
      "source_port_441",
      "source_port_442",
      "source_port_443",
      "source_port_444",
      "source_port_445",
      "source_port_446",
      "source_port_447",
      "source_port_448",
      "source_port_449",
      "source_port_450",
      "source_port_451",
      "source_port_452",
      "source_port_453",
      "source_port_454",
      "source_port_455",
      "source_port_456",
      "source_port_457",
      "source_port_458",
      "source_port_459",
      "source_port_460",
      "source_port_461",
      "source_port_462",
      "source_port_463",
      "source_port_464",
      "source_port_465",
      "source_port_466",
      "source_port_467",
      "source_port_468",
      "source_port_469",
      "source_port_470",
      "source_port_471",
      "source_port_472",
      "source_port_473",
      "source_port_474",
      "source_port_475",
      "source_port_476",
      "source_port_477",
      "source_port_478",
      "source_port_479",
      "source_port_480",
      "source_port_481",
      "source_port_482",
      "source_port_483",
      "source_port_484",
      "source_port_485",
      "source_port_486",
      "source_port_487",
      "source_port_488",
      "source_port_489",
      "source_port_490",
      "source_port_491",
      "source_port_492",
      "source_port_493",
      "source_port_494",
      "source_port_495",
      "source_port_496",
      "source_port_497",
      "source_port_498",
      "source_port_499",
      "source_port_500",
      "source_port_501",
      "source_port_502",
      "source_port_503",
      "source_port_504",
      "source_port_505",
      "source_port_506",
      "source_port_507",
      "source_port_508",
      "source_port_509",
      "source_port_510",
      "source_port_511",
      "source_port_512",
      "source_port_513",
      "source_port_514",
      "source_port_515",
      "source_port_516",
      "source_port_517",
      "source_port_518",
      "source_port_519",
      "source_port_520",
      "source_port_521",
      "source_port_522",
      "source_port_523",
      "source_port_524",
      "source_port_525",
      "source_port_526",
      "source_port_527",
      "source_port_528",
      "source_port_529",
      "source_port_530",
      "source_port_531",
      "source_port_532",
      "source_port_533",
      "source_port_534",
      "source_port_535",
      "source_port_536",
      "source_port_537",
      "source_port_538",
      "source_port_539",
      "source_port_540",
      "source_port_541",
      "source_port_542",
      "source_port_543",
      "source_port_544",
      "source_port_545",
      "source_port_546",
      "source_port_547",
      "source_port_548",
      "source_port_549",
      "source_port_550",
      "source_port_551",
      "source_port_552",
      "source_port_553",
      "source_port_554",
      "source_port_555",
      "source_port_556",
      "source_port_557",
      "source_port_558",
      "source_port_559",
      "source_port_560",
      "source_port_561",
      "source_port_562",
      "source_port_563",
      "source_port_564",
      "source_port_565",
      "source_port_566",
      "source_port_567",
      "source_port_568",
      "source_port_569",
      "source_port_570",
      "source_port_571",
      "source_port_572"
    ],
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_group",
    "source_group_id": "source_group_3",
    "name": "SOC_DIRECT_RAIL_MEMBERSHIP",
    "was_automatically_named": false,
    "parent_source_group_id": "source_group_4"
  },
  {
    "type": "source_group",
    "source_group_id": "source_group_4",
    "name": "SOC_DIRECT_DECOUPLING",
    "was_automatically_named": false,
    "parent_source_group_id": "source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_589",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_10",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_590",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_10",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_10",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDD_CORE_U19",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_591",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_592",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_593",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_0",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_0",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_594",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_595",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_596",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_1",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_1",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_597",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_11",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_598",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_11",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_11",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDD_CORE_U43",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_599",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_2",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_600",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_2",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_601",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_2",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_2",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_602",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_3",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_603",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_3",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_604",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_3",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_3",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_605",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_12",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_606",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_12",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_12",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDD_CORE_U40",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_607",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_4",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_608",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_4",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_4",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_4",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_610",
    "name": "top",
    "port_hints": [
      "top"
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    "source_component_id": "source_manually_placed_via_5",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_611",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_5",
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  },
  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_5",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_5",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_613",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
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    "source_component_id": "source_component_13",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_614",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
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    "source_component_id": "source_component_13",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_13",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDD_CORE_U38",
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  {
    "type": "source_port",
    "source_port_id": "source_port_615",
    "name": "top",
    "port_hints": [
      "top"
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    "source_component_id": "source_manually_placed_via_6",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_6",
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  {
    "type": "source_port",
    "source_port_id": "source_port_617",
    "name": "pin1",
    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_6",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_6",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
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  {
    "type": "source_port",
    "source_port_id": "source_port_618",
    "name": "top",
    "port_hints": [
      "top"
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    "source_component_id": "source_manually_placed_via_7",
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  {
    "type": "source_port",
    "source_port_id": "source_port_619",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_7",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_620",
    "name": "pin1",
    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_7",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_7",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
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  {
    "type": "source_port",
    "source_port_id": "source_port_621",
    "name": "pin1",
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    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
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    "source_component_id": "source_component_14",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
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  {
    "type": "source_port",
    "source_port_id": "source_port_622",
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    "pin_number": 2,
    "port_hints": [
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      "neg",
      "cathode",
      "2",
      "right"
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    "source_component_id": "source_component_14",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "name": "C_SOC_VDD_CORE_U41",
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  {
    "type": "source_port",
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    "name": "top",
    "port_hints": [
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    "source_component_id": "source_manually_placed_via_8",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "name": "bottom",
    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_8",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_8",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_8",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
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  {
    "type": "source_port",
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    "name": "top",
    "port_hints": [
      "top"
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    "source_component_id": "source_manually_placed_via_9",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_9",
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_628",
    "name": "pin1",
    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_9",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_9",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
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  {
    "type": "source_port",
    "source_port_id": "source_port_629",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
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    "source_component_id": "source_component_15",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_630",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
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    "source_component_id": "source_component_15",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "name": "C_SOC_VDD_CORE_U24",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_10",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "name": "bottom",
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      "bottom"
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    "source_component_id": "source_manually_placed_via_10",
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  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_10",
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  {
    "type": "source_manually_placed_via",
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    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_11",
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  {
    "type": "source_port",
    "source_port_id": "source_port_635",
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    "source_component_id": "source_manually_placed_via_11",
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  {
    "type": "source_port",
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    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_11",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
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  {
    "type": "source_port",
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    "port_hints": [
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      "pos",
      "anode",
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    "source_component_id": "source_component_16",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
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  {
    "type": "source_port",
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    "pin_number": 2,
    "port_hints": [
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      "neg",
      "cathode",
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      "right"
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    "source_component_id": "source_component_16",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_12",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_12",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_12",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_12",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_13",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_13",
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  },
  {
    "type": "source_port",
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    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_13",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
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    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
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  {
    "type": "source_port",
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    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
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    "source_component_id": "source_component_17",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
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  {
    "type": "source_port",
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    "pin_number": 2,
    "port_hints": [
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      "cathode",
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      "right"
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    "source_component_id": "source_component_17",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "name": "C_SOC_VDD_CORE_C324",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_14",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_14",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_14",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_14",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
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  {
    "type": "source_port",
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    "name": "top",
    "port_hints": [
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    "source_component_id": "source_manually_placed_via_15",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_15",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_15",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_15",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_653",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
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    "source_component_id": "source_component_18",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_654",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
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    "source_component_id": "source_component_18",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "ftype": "simple_capacitor",
    "name": "C_SOC_VDD_CORE_C312",
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    "max_decoupling_trace_length": 3.81,
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  {
    "type": "source_port",
    "source_port_id": "source_port_655",
    "name": "top",
    "port_hints": [
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    "source_component_id": "source_manually_placed_via_16",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_16",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_657",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_16",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_16",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
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  {
    "type": "source_port",
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    "name": "top",
    "port_hints": [
      "top"
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    "source_component_id": "source_manually_placed_via_17",
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  },
  {
    "type": "source_port",
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      "bottom"
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    "source_component_id": "source_manually_placed_via_17",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_17",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_17",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
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  {
    "type": "source_port",
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      "pin1",
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      "anode",
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    "source_component_id": "source_component_19",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_662",
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    "pin_number": 2,
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      "pin2",
      "neg",
      "cathode",
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      "right"
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    "source_component_id": "source_component_19",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "name": "C_SOC_VDD_CORE_C376",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_18",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_18",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_18",
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  {
    "type": "source_manually_placed_via",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_19",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_19",
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  {
    "type": "source_port",
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      "pin1"
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    "source_component_id": "source_manually_placed_via_19",
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  {
    "type": "source_manually_placed_via",
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  {
    "type": "source_port",
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  {
    "type": "source_port",
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    "pin_number": 2,
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      "neg",
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      "2",
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    "source_component_id": "source_component_20",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "name": "C_SOC_VDD_CORE_C316",
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  {
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    "source_component_id": "source_manually_placed_via_20",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_20",
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  {
    "type": "source_port",
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      "pin1"
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    "source_component_id": "source_manually_placed_via_20",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_21",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_21",
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  {
    "type": "source_port",
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    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_21",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_21",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
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  {
    "type": "source_port",
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    "port_hints": [
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      "pos",
      "anode",
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    "source_component_id": "source_component_21",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
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  {
    "type": "source_port",
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    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
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      "right"
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    "source_component_id": "source_component_21",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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  {
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    "source_component_id": "source_manually_placed_via_22",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_22",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_22",
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  {
    "type": "source_manually_placed_via",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_23",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_23",
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  {
    "type": "source_port",
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      "pin1"
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    "source_component_id": "source_manually_placed_via_23",
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  {
    "type": "source_manually_placed_via",
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  {
    "type": "source_port",
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    "source_component_id": "source_component_22",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
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  {
    "type": "source_port",
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    "pin_number": 2,
    "port_hints": [
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    "source_component_id": "source_component_22",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_24",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_24",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_24",
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  {
    "type": "source_manually_placed_via",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_25",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_25",
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  {
    "type": "source_port",
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    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_25",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
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  {
    "type": "source_port",
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      "anode",
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    "source_component_id": "source_component_23",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
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  {
    "type": "source_port",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "source_component_id": "source_manually_placed_via_26",
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  {
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    "source_component_id": "source_manually_placed_via_26",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_26",
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  {
    "type": "source_manually_placed_via",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_27",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_27",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_27",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
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    "source_net_id": "source_net_16"
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  {
    "type": "source_port",
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    "pin_number": 1,
    "port_hints": [
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      "pos",
      "anode",
      "1",
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    "source_component_id": "source_component_24",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
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  {
    "type": "source_port",
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    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
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      "neg",
      "cathode",
      "2",
      "right"
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    "source_component_id": "source_component_24",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "ftype": "simple_capacitor",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_28",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_28",
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  {
    "type": "source_port",
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    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_28",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_28",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
  },
  {
    "type": "source_port",
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    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_29",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_707",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_29",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_708",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_29",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_29",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_709",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_25",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_710",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_25",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_25",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDD_CORE_C332",
    "capacitance": 1e-7,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "0.1uF",
    "are_pins_interchangeable": true,
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_711",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_30",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_30",
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_713",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_30",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_30",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
  },
  {
    "type": "source_port",
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    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_31",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_715",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_31",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_716",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_31",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_31",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_717",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_26",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_718",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_26",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_26",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDD_CORE_C108",
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  {
    "type": "source_port",
    "source_port_id": "source_port_719",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_32",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_720",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_32",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_721",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_32",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_32",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_722",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_33",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_723",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_33",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_724",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_33",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_33",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_725",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_27",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_726",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_27",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_27",
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    "name": "C_SOC_VDD_CORE_C107",
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_727",
    "name": "top",
    "port_hints": [
      "top"
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    "source_component_id": "source_manually_placed_via_34",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_728",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_34",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_729",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_34",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_34",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_730",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_35",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_35",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_732",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_35",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_35",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_733",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_28",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_734",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_28",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
    "source_component_id": "source_component_28",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDD_CORE_C377",
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  {
    "type": "source_port",
    "source_port_id": "source_port_735",
    "name": "top",
    "port_hints": [
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    ],
    "source_component_id": "source_manually_placed_via_36",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_36",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_36",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
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    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_738",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_37",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_739",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_37",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_37",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_37",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
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    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_29",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
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  {
    "type": "source_port",
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    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
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    "source_component_id": "source_component_29",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "name": "C_SOC_VDD_CORE_C268",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_38",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_38",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_745",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_38",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_38",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_0"
  },
  {
    "type": "source_port",
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    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_39",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_39",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_748",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_39",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_39",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_749",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_30",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net39"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_750",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_30",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_30",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDDA_CORE_C291",
    "capacitance": 1e-7,
    "max_decoupling_trace_length": 3.81,
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    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_751",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_40",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_40",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_753",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_40",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_40",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_754",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_41",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_755",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_41",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
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    "type": "source_port",
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  {
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  {
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      "pin1",
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      "anode",
      "1",
      "left"
    ],
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    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_854",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_43",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_43",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD1V8_C341",
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_855",
    "name": "top",
    "port_hints": [
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    "source_component_id": "source_manually_placed_via_66",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_66",
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  },
  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_66",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_66",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_3"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_858",
    "name": "top",
    "port_hints": [
      "top"
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    "source_component_id": "source_manually_placed_via_67",
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_859",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_67",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_860",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_67",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_67",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_861",
    "name": "pin1",
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    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_862",
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    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
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    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
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    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD1V8_C320",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_68",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_68",
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_865",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_68",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_68",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_3"
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_69",
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  {
    "type": "source_port",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_69",
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  },
  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_69",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_69",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
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      "pin1",
      "pos",
      "anode",
      "1",
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    "source_component_id": "source_component_45",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
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      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
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    "source_component_id": "source_component_45",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
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    "ftype": "simple_capacitor",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_70",
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  {
    "type": "source_port",
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    "port_hints": [
      "bottom"
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    "source_component_id": "source_manually_placed_via_70",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_70",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_70",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_3"
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  {
    "type": "source_port",
    "source_port_id": "source_port_874",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_71",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_71",
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_876",
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    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_71",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_71",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
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      "anode",
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    "source_component_id": "source_component_46",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
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    "pin_number": 2,
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      "cathode",
      "2",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
    "source_component_id": "source_component_46",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD1V8_C295",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_72",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_72",
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  {
    "type": "source_port",
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    "port_hints": [
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    ],
    "source_component_id": "source_manually_placed_via_72",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_72",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_3"
  },
  {
    "type": "source_port",
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    "name": "top",
    "port_hints": [
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    ],
    "source_component_id": "source_manually_placed_via_73",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_883",
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    "port_hints": [
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    ],
    "source_component_id": "source_manually_placed_via_73",
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  {
    "type": "source_port",
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    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_73",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_73",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_885",
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      "pos",
      "anode",
      "1",
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    "source_component_id": "source_component_47",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
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    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
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    "source_component_id": "source_component_47",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
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  {
    "type": "source_component",
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    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD1V8_C103",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_74",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_74",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_74",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_3"
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  {
    "type": "source_port",
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    "port_hints": [
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    ],
    "source_component_id": "source_manually_placed_via_75",
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  {
    "type": "source_port",
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    "source_component_id": "source_manually_placed_via_75",
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  {
    "type": "source_port",
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    "port_hints": [
      "pin1"
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    "source_component_id": "source_manually_placed_via_75",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_manually_placed_via",
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    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
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  {
    "type": "source_port",
    "source_port_id": "source_port_893",
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    "port_hints": [
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      "pos",
      "anode",
      "1",
      "left"
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    "source_component_id": "source_component_48",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
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  {
    "type": "source_port",
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    "pin_number": 2,
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      "cathode",
      "2",
      "right"
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    "source_component_id": "source_component_48",
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    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
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    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD1V8_C95",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_76",
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  {
    "type": "source_port",
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    "port_hints": [
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    "source_component_id": "source_manually_placed_via_76",
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  },
  {
    "type": "source_port",
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    "port_hints": [
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    ],
    "source_component_id": "source_manually_placed_via_76",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_76",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_3"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_898",
    "name": "top",
    "port_hints": [
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    ],
    "source_component_id": "source_manually_placed_via_77",
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  },
  {
    "type": "source_port",
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    "port_hints": [
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    ],
    "source_component_id": "source_manually_placed_via_77",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_900",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_77",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_77",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_901",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_49",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_902",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_49",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_49",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD1V8_C314",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 15,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_903",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_78",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_904",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_78",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_905",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_78",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_78",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_3"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_906",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_79",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_907",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_79",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_908",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_79",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_79",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_909",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_50",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_910",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_50",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_50",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD3V3_C394",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_911",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_80",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_912",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_80",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_913",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_80",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_80",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_914",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_81",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_915",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_81",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_916",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_81",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_81",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_917",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_51",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_918",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_51",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_51",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD3V3_C395",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_919",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_82",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_920",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_82",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_921",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_82",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_82",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_922",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_83",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_923",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_83",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_924",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_83",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_83",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_925",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_52",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_926",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_52",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_52",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD3V3_C290",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_927",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_84",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_928",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_84",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_929",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_84",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_84",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_930",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_85",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_931",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_85",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_932",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_85",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_85",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_933",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_53",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_934",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_53",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_53",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD3V3_C402",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_935",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_86",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_936",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_86",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_937",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_86",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_86",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_938",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_87",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_939",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_87",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_940",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_87",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_87",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_941",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_54",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_942",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_54",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_54",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD3V3_C349",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_943",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_88",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_944",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_88",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_945",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_88",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_88",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_946",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_89",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_947",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_89",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_948",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_89",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_89",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_949",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_55",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_950",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_55",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_55",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD3V3_C408",
    "capacitance": 0.00001,
    "max_decoupling_trace_length": 15,
    "display_capacitance": "10uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_951",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_90",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_952",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_90",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_953",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_90",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_90",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_954",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_91",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_955",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_91",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_956",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_91",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_91",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_957",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_56",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_958",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_56",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_56",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_DVDD3V3_C334",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 15,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_959",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_92",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_960",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_92",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_961",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_92",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_92",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_962",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_93",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_963",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_93",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_964",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_93",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_93",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_965",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_57",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net40"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_966",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_57",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_57",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VPP_1V8_C98",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 15,
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    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_967",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_94",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_968",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_94",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_969",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_94",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_94",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_5"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_970",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_95",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_971",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_95",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_972",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_95",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_95",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_973",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_58",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net40"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_974",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_58",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_58",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VPP_1V8_C99",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 15,
    "display_capacitance": "1uF",
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_975",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_96",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_976",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_96",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_977",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_96",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_96",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_5"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_978",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_97",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_979",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_97",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_980",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_97",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_97",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_981",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_59",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net40"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_982",
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    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_59",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_59",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VPP_1V8_C104",
    "capacitance": 1e-7,
    "max_decoupling_trace_length": 15,
    "display_capacitance": "0.1uF",
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_983",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_98",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_984",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_98",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_985",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_98",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_98",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_5"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_986",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_99",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_987",
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    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_99",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_988",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_99",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_99",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_989",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_60",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net41"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_990",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_60",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_60",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDD_MMC1_SD_C289",
    "capacitance": 1e-7,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "0.1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
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    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_100",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_992",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_100",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_993",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_100",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_100",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_6"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_994",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_101",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_995",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_101",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_996",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_101",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_101",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_997",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_61",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net42"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_998",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_61",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_61",
    "ftype": "simple_capacitor",
    "name": "C_SOC_VDDSHV_SD_IO_C301",
    "capacitance": 1e-7,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "0.1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_999",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_102",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1000",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_102",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1001",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_102",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_102",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_7"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1002",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_103",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1003",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_103",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1004",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_103",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_103",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1005",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_62",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net43"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1006",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_62",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_62",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_VDD_RTC_C300",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1007",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_104",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1008",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_104",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1009",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_104",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_104",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_8"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1010",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_105",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1011",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_105",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1012",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_105",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_105",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1013",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_63",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net44"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1014",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_63",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_63",
    "ftype": "simple_capacitor",
    "name": "C_SOC_SOC_VDDS_RTC_1V8_C292",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1015",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_106",
    "subcircuit_id": "subcircuit_source_group_2"
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  {
    "type": "source_port",
    "source_port_id": "source_port_1016",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_106",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1017",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_106",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_106",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_9"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1018",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_107",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1019",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_107",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1020",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_107",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_107",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1021",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_64",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net45"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1022",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_64",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_64",
    "ftype": "simple_capacitor",
    "name": "C_SOC_CAP_VDDS_MMC0_C339",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
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  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1023",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_108",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1024",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_108",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1025",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_108",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_108",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_10"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1026",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_109",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1027",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_109",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1028",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_109",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_109",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1029",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_65",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net46"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1030",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_65",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_65",
    "ftype": "simple_capacitor",
    "name": "C_SOC_CAP_VDDS_MMC1_C294",
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    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
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    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1031",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_110",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1032",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_110",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1033",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_110",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_110",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_11"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1034",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_111",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1035",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_111",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1036",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_111",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_111",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1037",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_66",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net47"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1038",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_66",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_66",
    "ftype": "simple_capacitor",
    "name": "C_SOC_CAP_VDDS_MMC2_C310",
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    "max_decoupling_trace_length": 3.81,
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    "source_group_id": "source_group_4"
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  {
    "type": "source_port",
    "source_port_id": "source_port_1039",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_112",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
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    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_112",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1041",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_112",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_112",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_12"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1042",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_113",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1043",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_113",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1044",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_113",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_113",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1045",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_67",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net48"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1046",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_67",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_67",
    "ftype": "simple_capacitor",
    "name": "C_SOC_CAP_VDDS_GPMC_C323",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1047",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_114",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1048",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_114",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1049",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_114",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_114",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_13"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1050",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_115",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1051",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_115",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1052",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_115",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_115",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1053",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_68",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net49"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1054",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_68",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_68",
    "ftype": "simple_capacitor",
    "name": "C_SOC_CAP_VDDS_GENERAL1_C338",
    "capacitance": 0.000001,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1055",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_116",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1056",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_116",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1057",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_116",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_116",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_14"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1058",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_117",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1059",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_117",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1060",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_117",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_117",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1061",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_69",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net50"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1062",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_69",
    "subcircuit_id": "subcircuit_source_group_2",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_69",
    "ftype": "simple_capacitor",
    "name": "C_SOC_CAP_VDDSHV_MMC_C286",
    "capacitance": 0.0000033,
    "max_decoupling_trace_length": 3.81,
    "display_capacitance": "3.3uF",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_4"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1063",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_118",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1064",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_118",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1065",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_118",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_118",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_15"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1066",
    "name": "top",
    "port_hints": [
      "top"
    ],
    "source_component_id": "source_manually_placed_via_119",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1067",
    "name": "bottom",
    "port_hints": [
      "bottom"
    ],
    "source_component_id": "source_manually_placed_via_119",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1068",
    "name": "pin1",
    "port_hints": [
      "pin1"
    ],
    "source_component_id": "source_manually_placed_via_119",
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_manually_placed_via",
    "source_manually_placed_via_id": "source_manually_placed_via_119",
    "source_group_id": "source_group_4",
    "subcircuit_id": "subcircuit_source_group_2",
    "source_net_id": "source_net_16"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_261",
    "connected_source_port_ids": [
      "source_port_97"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_J9_PDN_MEMBERSHIP",
    "display_name": ".U1 > .J9 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_262",
    "connected_source_port_ids": [
      "source_port_98"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_J11_PDN_MEMBERSHIP",
    "display_name": ".U1 > .J11 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_263",
    "connected_source_port_ids": [
      "source_port_99"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_J13_PDN_MEMBERSHIP",
    "display_name": ".U1 > .J13 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_264",
    "connected_source_port_ids": [
      "source_port_100"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_J15_PDN_MEMBERSHIP",
    "display_name": ".U1 > .J15 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_265",
    "connected_source_port_ids": [
      "source_port_101"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_K10_PDN_MEMBERSHIP",
    "display_name": ".U1 > .K10 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_266",
    "connected_source_port_ids": [
      "source_port_102"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_K14_PDN_MEMBERSHIP",
    "display_name": ".U1 > .K14 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_267",
    "connected_source_port_ids": [
      "source_port_103"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_L15_PDN_MEMBERSHIP",
    "display_name": ".U1 > .L15 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_268",
    "connected_source_port_ids": [
      "source_port_104"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_M14_PDN_MEMBERSHIP",
    "display_name": ".U1 > .M14 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_269",
    "connected_source_port_ids": [
      "source_port_105"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_N15_PDN_MEMBERSHIP",
    "display_name": ".U1 > .N15 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_270",
    "connected_source_port_ids": [
      "source_port_106"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_P10_PDN_MEMBERSHIP",
    "display_name": ".U1 > .P10 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_271",
    "connected_source_port_ids": [
      "source_port_107"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_P12_PDN_MEMBERSHIP",
    "display_name": ".U1 > .P12 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_272",
    "connected_source_port_ids": [
      "source_port_108"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_P14_PDN_MEMBERSHIP",
    "display_name": ".U1 > .P14 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_273",
    "connected_source_port_ids": [
      "source_port_109"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_R9_PDN_MEMBERSHIP",
    "display_name": ".U1 > .R9 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_274",
    "connected_source_port_ids": [
      "source_port_110"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_R11_PDN_MEMBERSHIP",
    "display_name": ".U1 > .R11 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_275",
    "connected_source_port_ids": [
      "source_port_111"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_M10_PDN_MEMBERSHIP",
    "display_name": ".U1 > .M10 to net.VDD_CORE",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net36"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_276",
    "connected_source_port_ids": [
      "source_port_117"
    ],
    "connected_source_net_ids": [
      "source_net_1"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_G14_PDN_MEMBERSHIP",
    "display_name": ".U1 > .G14 to net.VDDA_1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_277",
    "connected_source_port_ids": [
      "source_port_118"
    ],
    "connected_source_net_ids": [
      "source_net_1"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_T12_PDN_MEMBERSHIP",
    "display_name": ".U1 > .T12 to net.VDDA_1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_278",
    "connected_source_port_ids": [
      "source_port_119"
    ],
    "connected_source_net_ids": [
      "source_net_1"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_R16_PDN_MEMBERSHIP",
    "display_name": ".U1 > .R16 to net.VDDA_1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_279",
    "connected_source_port_ids": [
      "source_port_120"
    ],
    "connected_source_net_ids": [
      "source_net_1"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_N17_PDN_MEMBERSHIP",
    "display_name": ".U1 > .N17 to net.VDDA_1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_280",
    "connected_source_port_ids": [
      "source_port_121"
    ],
    "connected_source_net_ids": [
      "source_net_1"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_L11_PDN_MEMBERSHIP",
    "display_name": ".U1 > .L11 to net.VDDA_1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_281",
    "connected_source_port_ids": [
      "source_port_122"
    ],
    "connected_source_net_ids": [
      "source_net_1"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_K12_PDN_MEMBERSHIP",
    "display_name": ".U1 > .K12 to net.VDDA_1V8",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net37"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_282",
    "connected_source_port_ids": [
      "source_port_123"
    ],
    "connected_source_net_ids": [
      "source_net_2"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_U12_PDN_MEMBERSHIP",
    "display_name": ".U1 > .U12 to net.SOC_DVDD3V3",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_283",
    "connected_source_port_ids": [
      "source_port_124"
    ],
    "connected_source_net_ids": [
      "source_net_2"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_J16_PDN_MEMBERSHIP",
    "display_name": ".U1 > .J16 to net.SOC_DVDD3V3",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_284",
    "connected_source_port_ids": [
      "source_port_125"
    ],
    "connected_source_net_ids": [
      "source_net_2"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_L17_PDN_MEMBERSHIP",
    "display_name": ".U1 > .L17 to net.SOC_DVDD3V3",
    "subcircuit_connectivity_map_key": "AM62L_LPDDR4_RIGHT_connectivity_net38"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_285",
    "connected_source_port_ids": [
      "source_port_126"
    ],
    "connected_source_net_ids": [
      "source_net_2"
    ],
    "subcircuit_id": "subcircuit_source_group_2",
    "name": "U1_G10_PDN_MEMBERSHIP",
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    "cad_component_id": "cad_component_64",
    "position": {
      "x": -13,
      "y": 4.7,
      "z": -0.7
    },
    "rotation": {
      "x": 0,
      "y": 180,
      "z": 0
    },
    "pcb_component_id": "pcb_component_172",
    "source_component_id": "source_component_64",
    "model_origin_alignment": "center_of_component_on_board_surface",
    "anchor_alignment": "center_of_component_on_board_surface",
    "footprinter_string": "cap0201_nosilkscreen"
  },
  {
    "type": "cad_component",
    "cad_component_id": "cad_component_65",
    "position": {
      "x": -11.8,
      "y": -6.1,
      "z": -0.7
    },
    "rotation": {
      "x": 0,
      "y": 180,
      "z": 90
    },
    "pcb_component_id": "pcb_component_175",
    "source_component_id": "source_component_65",
    "model_origin_alignment": "center_of_component_on_board_surface",
    "anchor_alignment": "center_of_component_on_board_surface",
    "footprinter_string": "cap0201_nosilkscreen"
  },
  {
    "type": "cad_component",
    "cad_component_id": "cad_component_66",
    "position": {
      "x": -6.3,
      "y": -1.3,
      "z": -0.7
    },
    "rotation": {
      "x": 0,
      "y": 180,
      "z": 0
    },
    "pcb_component_id": "pcb_component_178",
    "source_component_id": "source_component_66",
    "model_origin_alignment": "center_of_component_on_board_surface",
    "anchor_alignment": "center_of_component_on_board_surface",
    "footprinter_string": "cap0201_nosilkscreen"
  },
  {
    "type": "cad_component",
    "cad_component_id": "cad_component_67",
    "position": {
      "x": -6.7,
      "y": -2.2,
      "z": -0.7
    },
    "rotation": {
      "x": 0,
      "y": 180,
      "z": 90
    },
    "pcb_component_id": "pcb_component_181",
    "source_component_id": "source_component_67",
    "model_origin_alignment": "center_of_component_on_board_surface",
    "anchor_alignment": "center_of_component_on_board_surface",
    "footprinter_string": "cap0201_nosilkscreen"
  },
  {
    "type": "cad_component",
    "cad_component_id": "cad_component_68",
    "position": {
      "x": -9.1,
      "y": 6.2,
      "z": -0.7
    },
    "rotation": {
      "x": 0,
      "y": 180,
      "z": 180
    },
    "pcb_component_id": "pcb_component_184",
    "source_component_id": "source_component_68",
    "model_origin_alignment": "center_of_component_on_board_surface",
    "anchor_alignment": "center_of_component_on_board_surface",
    "footprinter_string": "cap0201_nosilkscreen"
  },
  {
    "type": "cad_component",
    "cad_component_id": "cad_component_69",
    "position": {
      "x": -6.8,
      "y": -5.6,
      "z": -0.7
    },
    "rotation": {
      "x": 0,
      "y": 180,
      "z": 90
    },
    "pcb_component_id": "pcb_component_187",
    "source_component_id": "source_component_69",
    "model_origin_alignment": "center_of_component_on_board_surface",
    "anchor_alignment": "center_of_component_on_board_surface",
    "footprinter_string": "cap0201_nosilkscreen"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.J9] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_97"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_0"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.J11] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_98"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_1"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.J13] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_99"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_2"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.J15] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_100"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_3"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.K10] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_101"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_4"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.K14] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_102"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_5"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.L15] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_103"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_6"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.M14] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_104"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_7"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.N15] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_105"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_8"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.P10] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_106"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_9"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.P12] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_107"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_10"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.P14] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_108"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_11"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.R9] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_109"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_12"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.R11] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_110"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_13"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.M10] is not connected to net [VDD_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_111"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_14"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.G14] is not connected to net [VDDA_1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_117"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_15"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.T12] is not connected to net [VDDA_1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_118"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_16"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.R16] is not connected to net [VDDA_1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_119"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_17"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.N17] is not connected to net [VDDA_1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_120"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_18"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.L11] is not connected to net [VDDA_1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_121"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_19"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.K12] is not connected to net [VDDA_1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_122"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_20"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.U12] is not connected to net [SOC_DVDD3V3] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_123"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_21"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.J16] is not connected to net [SOC_DVDD3V3] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_124"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_22"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.L17] is not connected to net [SOC_DVDD3V3] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_125"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_23"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.G10] is not connected to net [SOC_DVDD3V3] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_126"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_24"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.H10] is not connected to net [SOC_DVDD3V3] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_127"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_25"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.H8] is not connected to net [SOC_DVDD1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_128"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_26"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.M17] is not connected to net [SOC_DVDD1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_129"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_27"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.T14] is not connected to net [SOC_DVDD1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_130"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_28"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.H16] is not connected to net [SOC_DVDD1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_131"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_29"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.P16] is not connected to net [SOC_DVDD1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_132"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_30"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.U11] is not connected to net [VDDA_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_133"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_31"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.H12] is not connected to net [VDDA_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_134"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_32"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.G13] is not connected to net [VDDA_CORE] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_135"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_33"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.N18] is not connected to net [VPP_1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_136"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_34"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.U16] is not connected to net [VDD_MMC1_SD] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_137"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_35"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.T10] is not connected to net [VDDSHV_SD_IO] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_138"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_36"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.T17] is not connected to net [SOC_VDD_RTC] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_139"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_37"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.T18] is not connected to net [SOC_VDDS_RTC_1V8] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_140"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_38"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.J8] is not connected to net [CAP_VDDS_MMC0] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_141"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_39"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.U9] is not connected to net [CAP_VDDS_MMC1] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_142"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_40"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.M16] is not connected to net [CAP_VDDS_MMC2] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_143"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_41"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.K16] is not connected to net [CAP_VDDS_GPMC] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_144"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_42"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.G11] is not connected to net [CAP_VDDS_GENERAL1] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_145"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_43"
  },
  {
    "type": "pcb_port_not_connected_error",
    "message": "Port [U1.T16] is not connected to net [CAP_VDDSHV_MMC] by a PCB trace.",
    "error_type": "pcb_port_not_connected_error",
    "pcb_port_ids": [
      "pcb_port_146"
    ],
    "pcb_component_ids": [
      "pcb_component_0"
    ],
    "pcb_port_not_connected_error_id": "pcb_port_not_connected_error_44"
  },
  {
    "type": "source_component_pins_underspecified_warning",
    "source_component_pins_underspecified_warning_id": "source_component_pins_underspecified_warning_1",
    "warning_type": "source_component_pins_underspecified_warning",
    "message": "All pins on U2 are underspecified (no pinAttributes set)",
    "source_component_id": "source_component_1",
    "source_port_ids": [
      "source_port_373",
      "source_port_374",
      "source_port_375",
      "source_port_376",
      "source_port_377",
      "source_port_378",
      "source_port_379",
      "source_port_380",
      "source_port_381",
      "source_port_382",
      "source_port_383",
      "source_port_384",
      "source_port_385",
      "source_port_386",
      "source_port_387",
      "source_port_388",
      "source_port_389",
      "source_port_390",
      "source_port_391",
      "source_port_392",
      "source_port_393",
      "source_port_394",
      "source_port_395",
      "source_port_396",
      "source_port_397",
      "source_port_398",
      "source_port_399",
      "source_port_400",
      "source_port_401",
      "source_port_402",
      "source_port_403",
      "source_port_404",
      "source_port_405",
      "source_port_406",
      "source_port_407",
      "source_port_408",
      "source_port_409",
      "source_port_410",
      "source_port_411",
      "source_port_412",
      "source_port_413",
      "source_port_414",
      "source_port_415",
      "source_port_416",
      "source_port_417",
      "source_port_418",
      "source_port_419",
      "source_port_420",
      "source_port_421",
      "source_port_422",
      "source_port_423",
      "source_port_424",
      "source_port_425",
      "source_port_426",
      "source_port_427",
      "source_port_428",
      "source_port_429",
      "source_port_430",
      "source_port_431",
      "source_port_432",
      "source_port_433",
      "source_port_434",
      "source_port_435",
      "source_port_436",
      "source_port_437",
      "source_port_438",
      "source_port_439",
      "source_port_440",
      "source_port_441",
      "source_port_442",
      "source_port_443",
      "source_port_444",
      "source_port_445",
      "source_port_446",
      "source_port_447",
      "source_port_448",
      "source_port_449",
      "source_port_450",
      "source_port_451",
      "source_port_452",
      "source_port_453",
      "source_port_454",
      "source_port_455",
      "source_port_456",
      "source_port_457",
      "source_port_458",
      "source_port_459",
      "source_port_460",
      "source_port_461",
      "source_port_462",
      "source_port_463",
      "source_port_464",
      "source_port_465",
      "source_port_466",
      "source_port_467",
      "source_port_468",
      "source_port_469",
      "source_port_470",
      "source_port_471",
      "source_port_472",
      "source_port_473",
      "source_port_474",
      "source_port_475",
      "source_port_476",
      "source_port_477",
      "source_port_478",
      "source_port_479",
      "source_port_480",
      "source_port_481",
      "source_port_482",
      "source_port_483",
      "source_port_484",
      "source_port_485",
      "source_port_486",
      "source_port_487",
      "source_port_488",
      "source_port_489",
      "source_port_490",
      "source_port_491",
      "source_port_492",
      "source_port_493",
      "source_port_494",
      "source_port_495",
      "source_port_496",
      "source_port_497",
      "source_port_498",
      "source_port_499",
      "source_port_500",
      "source_port_501",
      "source_port_502",
      "source_port_503",
      "source_port_504",
      "source_port_505",
      "source_port_506",
      "source_port_507",
      "source_port_508",
      "source_port_509",
      "source_port_510",
      "source_port_511",
      "source_port_512",
      "source_port_513",
      "source_port_514",
      "source_port_515",
      "source_port_516",
      "source_port_517",
      "source_port_518",
      "source_port_519",
      "source_port_520",
      "source_port_521",
      "source_port_522",
      "source_port_523",
      "source_port_524",
      "source_port_525",
      "source_port_526",
      "source_port_527",
      "source_port_528",
      "source_port_529",
      "source_port_530",
      "source_port_531",
      "source_port_532",
      "source_port_533",
      "source_port_534",
      "source_port_535",
      "source_port_536",
      "source_port_537",
      "source_port_538",
      "source_port_539",
      "source_port_540",
      "source_port_541",
      "source_port_542",
      "source_port_543",
      "source_port_544",
      "source_port_545",
      "source_port_546",
      "source_port_547",
      "source_port_548",
      "source_port_549",
      "source_port_550",
      "source_port_551",
      "source_port_552",
      "source_port_553",
      "source_port_554",
      "source_port_555",
      "source_port_556",
      "source_port_557",
      "source_port_558",
      "source_port_559",
      "source_port_560",
      "source_port_561",
      "source_port_562",
      "source_port_563",
      "source_port_564",
      "source_port_565",
      "source_port_566",
      "source_port_567",
      "source_port_568",
      "source_port_569",
      "source_port_570",
      "source_port_571",
      "source_port_572"
    ],
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_no_power_pin_defined_warning",
    "source_no_power_pin_defined_warning_id": "source_no_power_pin_defined_warning_1",
    "warning_type": "source_no_power_pin_defined_warning",
    "message": "U2 has no pin with requires_power=true",
    "source_component_id": "source_component_1",
    "source_port_ids": [
      "source_port_373",
      "source_port_374",
      "source_port_375",
      "source_port_376",
      "source_port_377",
      "source_port_378",
      "source_port_379",
      "source_port_380",
      "source_port_381",
      "source_port_382",
      "source_port_383",
      "source_port_384",
      "source_port_385",
      "source_port_386",
      "source_port_387",
      "source_port_388",
      "source_port_389",
      "source_port_390",
      "source_port_391",
      "source_port_392",
      "source_port_393",
      "source_port_394",
      "source_port_395",
      "source_port_396",
      "source_port_397",
      "source_port_398",
      "source_port_399",
      "source_port_400",
      "source_port_401",
      "source_port_402",
      "source_port_403",
      "source_port_404",
      "source_port_405",
      "source_port_406",
      "source_port_407",
      "source_port_408",
      "source_port_409",
      "source_port_410",
      "source_port_411",
      "source_port_412",
      "source_port_413",
      "source_port_414",
      "source_port_415",
      "source_port_416",
      "source_port_417",
      "source_port_418",
      "source_port_419",
      "source_port_420",
      "source_port_421",
      "source_port_422",
      "source_port_423",
      "source_port_424",
      "source_port_425",
      "source_port_426",
      "source_port_427",
      "source_port_428",
      "source_port_429",
      "source_port_430",
      "source_port_431",
      "source_port_432",
      "source_port_433",
      "source_port_434",
      "source_port_435",
      "source_port_436",
      "source_port_437",
      "source_port_438",
      "source_port_439",
      "source_port_440",
      "source_port_441",
      "source_port_442",
      "source_port_443",
      "source_port_444",
      "source_port_445",
      "source_port_446",
      "source_port_447",
      "source_port_448",
      "source_port_449",
      "source_port_450",
      "source_port_451",
      "source_port_452",
      "source_port_453",
      "source_port_454",
      "source_port_455",
      "source_port_456",
      "source_port_457",
      "source_port_458",
      "source_port_459",
      "source_port_460",
      "source_port_461",
      "source_port_462",
      "source_port_463",
      "source_port_464",
      "source_port_465",
      "source_port_466",
      "source_port_467",
      "source_port_468",
      "source_port_469",
      "source_port_470",
      "source_port_471",
      "source_port_472",
      "source_port_473",
      "source_port_474",
      "source_port_475",
      "source_port_476",
      "source_port_477",
      "source_port_478",
      "source_port_479",
      "source_port_480",
      "source_port_481",
      "source_port_482",
      "source_port_483",
      "source_port_484",
      "source_port_485",
      "source_port_486",
      "source_port_487",
      "source_port_488",
      "source_port_489",
      "source_port_490",
      "source_port_491",
      "source_port_492",
      "source_port_493",
      "source_port_494",
      "source_port_495",
      "source_port_496",
      "source_port_497",
      "source_port_498",
      "source_port_499",
      "source_port_500",
      "source_port_501",
      "source_port_502",
      "source_port_503",
      "source_port_504",
      "source_port_505",
      "source_port_506",
      "source_port_507",
      "source_port_508",
      "source_port_509",
      "source_port_510",
      "source_port_511",
      "source_port_512",
      "source_port_513",
      "source_port_514",
      "source_port_515",
      "source_port_516",
      "source_port_517",
      "source_port_518",
      "source_port_519",
      "source_port_520",
      "source_port_521",
      "source_port_522",
      "source_port_523",
      "source_port_524",
      "source_port_525",
      "source_port_526",
      "source_port_527",
      "source_port_528",
      "source_port_529",
      "source_port_530",
      "source_port_531",
      "source_port_532",
      "source_port_533",
      "source_port_534",
      "source_port_535",
      "source_port_536",
      "source_port_537",
      "source_port_538",
      "source_port_539",
      "source_port_540",
      "source_port_541",
      "source_port_542",
      "source_port_543",
      "source_port_544",
      "source_port_545",
      "source_port_546",
      "source_port_547",
      "source_port_548",
      "source_port_549",
      "source_port_550",
      "source_port_551",
      "source_port_552",
      "source_port_553",
      "source_port_554",
      "source_port_555",
      "source_port_556",
      "source_port_557",
      "source_port_558",
      "source_port_559",
      "source_port_560",
      "source_port_561",
      "source_port_562",
      "source_port_563",
      "source_port_564",
      "source_port_565",
      "source_port_566",
      "source_port_567",
      "source_port_568",
      "source_port_569",
      "source_port_570",
      "source_port_571",
      "source_port_572"
    ],
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_no_ground_pin_defined_warning",
    "source_no_ground_pin_defined_warning_id": "source_no_ground_pin_defined_warning_2",
    "warning_type": "source_no_ground_pin_defined_warning",
    "message": "U1 has no pin with requires_ground=true",
    "source_component_id": "source_component_0",
    "source_port_ids": [
      "source_port_0",
      "source_port_1",
      "source_port_2",
      "source_port_3",
      "source_port_4",
      "source_port_5",
      "source_port_6",
      "source_port_7",
      "source_port_8",
      "source_port_9",
      "source_port_10",
      "source_port_11",
      "source_port_12",
      "source_port_13",
      "source_port_14",
      "source_port_15",
      "source_port_16",
      "source_port_17",
      "source_port_18",
      "source_port_19",
      "source_port_20",
      "source_port_21",
      "source_port_22",
      "source_port_23",
      "source_port_24",
      "source_port_25",
      "source_port_26",
      "source_port_27",
      "source_port_28",
      "source_port_29",
      "source_port_30",
      "source_port_31",
      "source_port_32",
      "source_port_33",
      "source_port_34",
      "source_port_35",
      "source_port_36",
      "source_port_37",
      "source_port_38",
      "source_port_39",
      "source_port_40",
      "source_port_41",
      "source_port_42",
      "source_port_43",
      "source_port_44",
      "source_port_45",
      "source_port_46",
      "source_port_47",
      "source_port_48",
      "source_port_49",
      "source_port_50",
      "source_port_51",
      "source_port_52",
      "source_port_53",
      "source_port_54",
      "source_port_55",
      "source_port_56",
      "source_port_57",
      "source_port_58",
      "source_port_59",
      "source_port_60",
      "source_port_61",
      "source_port_62",
      "source_port_63",
      "source_port_64",
      "source_port_65",
      "source_port_66",
      "source_port_67",
      "source_port_68",
      "source_port_69",
      "source_port_70",
      "source_port_71",
      "source_port_72",
      "source_port_73",
      "source_port_74",
      "source_port_75",
      "source_port_76",
      "source_port_77",
      "source_port_78",
      "source_port_79",
      "source_port_80",
      "source_port_81",
      "source_port_82",
      "source_port_83",
      "source_port_84",
      "source_port_85",
      "source_port_86",
      "source_port_87",
      "source_port_88",
      "source_port_89",
      "source_port_90",
      "source_port_91",
      "source_port_92",
      "source_port_93",
      "source_port_94",
      "source_port_95",
      "source_port_96",
      "source_port_97",
      "source_port_98",
      "source_port_99",
      "source_port_100",
      "source_port_101",
      "source_port_102",
      "source_port_103",
      "source_port_104",
      "source_port_105",
      "source_port_106",
      "source_port_107",
      "source_port_108",
      "source_port_109",
      "source_port_110",
      "source_port_111",
      "source_port_112",
      "source_port_113",
      "source_port_114",
      "source_port_115",
      "source_port_116",
      "source_port_117",
      "source_port_118",
      "source_port_119",
      "source_port_120",
      "source_port_121",
      "source_port_122",
      "source_port_123",
      "source_port_124",
      "source_port_125",
      "source_port_126",
      "source_port_127",
      "source_port_128",
      "source_port_129",
      "source_port_130",
      "source_port_131",
      "source_port_132",
      "source_port_133",
      "source_port_134",
      "source_port_135",
      "source_port_136",
      "source_port_137",
      "source_port_138",
      "source_port_139",
      "source_port_140",
      "source_port_141",
      "source_port_142",
      "source_port_143",
      "source_port_144",
      "source_port_145",
      "source_port_146",
      "source_port_147",
      "source_port_148",
      "source_port_149",
      "source_port_150",
      "source_port_151",
      "source_port_152",
      "source_port_153",
      "source_port_154",
      "source_port_155",
      "source_port_156",
      "source_port_157",
      "source_port_158",
      "source_port_159",
      "source_port_160",
      "source_port_161",
      "source_port_162",
      "source_port_163",
      "source_port_164",
      "source_port_165",
      "source_port_166",
      "source_port_167",
      "source_port_168",
      "source_port_169",
      "source_port_170",
      "source_port_171",
      "source_port_172",
      "source_port_173",
      "source_port_174",
      "source_port_175",
      "source_port_176",
      "source_port_177",
      "source_port_178",
      "source_port_179",
      "source_port_180",
      "source_port_181",
      "source_port_182",
      "source_port_183",
      "source_port_184",
      "source_port_185",
      "source_port_186",
      "source_port_187",
      "source_port_188",
      "source_port_189",
      "source_port_190",
      "source_port_191",
      "source_port_192",
      "source_port_193",
      "source_port_194",
      "source_port_195",
      "source_port_196",
      "source_port_197",
      "source_port_198",
      "source_port_199",
      "source_port_200",
      "source_port_201",
      "source_port_202",
      "source_port_203",
      "source_port_204",
      "source_port_205",
      "source_port_206",
      "source_port_207",
      "source_port_208",
      "source_port_209",
      "source_port_210",
      "source_port_211",
      "source_port_212",
      "source_port_213",
      "source_port_214",
      "source_port_215",
      "source_port_216",
      "source_port_217",
      "source_port_218",
      "source_port_219",
      "source_port_220",
      "source_port_221",
      "source_port_222",
      "source_port_223",
      "source_port_224",
      "source_port_225",
      "source_port_226",
      "source_port_227",
      "source_port_228",
      "source_port_229",
      "source_port_230",
      "source_port_231",
      "source_port_232",
      "source_port_233",
      "source_port_234",
      "source_port_235",
      "source_port_236",
      "source_port_237",
      "source_port_238",
      "source_port_239",
      "source_port_240",
      "source_port_241",
      "source_port_242",
      "source_port_243",
      "source_port_244",
      "source_port_245",
      "source_port_246",
      "source_port_247",
      "source_port_248",
      "source_port_249",
      "source_port_250",
      "source_port_251",
      "source_port_252",
      "source_port_253",
      "source_port_254",
      "source_port_255",
      "source_port_256",
      "source_port_257",
      "source_port_258",
      "source_port_259",
      "source_port_260",
      "source_port_261",
      "source_port_262",
      "source_port_263",
      "source_port_264",
      "source_port_265",
      "source_port_266",
      "source_port_267",
      "source_port_268",
      "source_port_269",
      "source_port_270",
      "source_port_271",
      "source_port_272",
      "source_port_273",
      "source_port_274",
      "source_port_275",
      "source_port_276",
      "source_port_277",
      "source_port_278",
      "source_port_279",
      "source_port_280",
      "source_port_281",
      "source_port_282",
      "source_port_283",
      "source_port_284",
      "source_port_285",
      "source_port_286",
      "source_port_287",
      "source_port_288",
      "source_port_289",
      "source_port_290",
      "source_port_291",
      "source_port_292",
      "source_port_293",
      "source_port_294",
      "source_port_295",
      "source_port_296",
      "source_port_297",
      "source_port_298",
      "source_port_299",
      "source_port_300",
      "source_port_301",
      "source_port_302",
      "source_port_303",
      "source_port_304",
      "source_port_305",
      "source_port_306",
      "source_port_307",
      "source_port_308",
      "source_port_309",
      "source_port_310",
      "source_port_311",
      "source_port_312",
      "source_port_313",
      "source_port_314",
      "source_port_315",
      "source_port_316",
      "source_port_317",
      "source_port_318",
      "source_port_319",
      "source_port_320",
      "source_port_321",
      "source_port_322",
      "source_port_323",
      "source_port_324",
      "source_port_325",
      "source_port_326",
      "source_port_327",
      "source_port_328",
      "source_port_329",
      "source_port_330",
      "source_port_331",
      "source_port_332",
      "source_port_333",
      "source_port_334",
      "source_port_335",
      "source_port_336",
      "source_port_337",
      "source_port_338",
      "source_port_339",
      "source_port_340",
      "source_port_341",
      "source_port_342",
      "source_port_343",
      "source_port_344",
      "source_port_345",
      "source_port_346",
      "source_port_347",
      "source_port_348",
      "source_port_349",
      "source_port_350",
      "source_port_351",
      "source_port_352",
      "source_port_353",
      "source_port_354",
      "source_port_355",
      "source_port_356",
      "source_port_357",
      "source_port_358",
      "source_port_359",
      "source_port_360",
      "source_port_361",
      "source_port_362",
      "source_port_363",
      "source_port_364",
      "source_port_365",
      "source_port_366",
      "source_port_367",
      "source_port_368",
      "source_port_369",
      "source_port_370",
      "source_port_371",
      "source_port_372"
    ],
    "subcircuit_id": "subcircuit_source_group_2"
  },
  {
    "type": "source_no_ground_pin_defined_warning",
    "source_no_ground_pin_defined_warning_id": "source_no_ground_pin_defined_warning_3",
    "warning_type": "source_no_ground_pin_defined_warning",
    "message": "U2 has no pin with requires_ground=true",
    "source_component_id": "source_component_1",
    "source_port_ids": [
      "source_port_373",
      "source_port_374",
      "source_port_375",
      "source_port_376",
      "source_port_377",
      "source_port_378",
      "source_port_379",
      "source_port_380",
      "source_port_381",
      "source_port_382",
      "source_port_383",
      "source_port_384",
      "source_port_385",
      "source_port_386",
      "source_port_387",
      "source_port_388",
      "source_port_389",
      "source_port_390",
      "source_port_391",
      "source_port_392",
      "source_port_393",
      "source_port_394",
      "source_port_395",
      "source_port_396",
      "source_port_397",
      "source_port_398",
      "source_port_399",
      "source_port_400",
      "source_port_401",
      "source_port_402",
      "source_port_403",
      "source_port_404",
      "source_port_405",
      "source_port_406",
      "source_port_407",
      "source_port_408",
      "source_port_409",
      "source_port_410",
      "source_port_411",
      "source_port_412",
      "source_port_413",
      "source_port_414",
      "source_port_415",
      "source_port_416",
      "source_port_417",
      "source_port_418",
      "source_port_419",
      "source_port_420",
      "source_port_421",
      "source_port_422",
      "source_port_423",
      "source_port_424",
      "source_port_425",
      "source_port_426",
      "source_port_427",
      "source_port_428",
      "source_port_429",
      "source_port_430",
      "source_port_431",
      "source_port_432",
      "source_port_433",
      "source_port_434",
      "source_port_435",
      "source_port_436",
      "source_port_437",
      "source_port_438",
      "source_port_439",
      "source_port_440",
      "source_port_441",
      "source_port_442",
      "source_port_443",
      "source_port_444",
      "source_port_445",
      "source_port_446",
      "source_port_447",
      "source_port_448",
      "source_port_449",
      "source_port_450",
      "source_port_451",
      "source_port_452",
      "source_port_453",
      "source_port_454",
      "source_port_455",
      "source_port_456",
      "source_port_457",
      "source_port_458",
      "source_port_459",
      "source_port_460",
      "source_port_461",
      "source_port_462",
      "source_port_463",
      "source_port_464",
      "source_port_465",
      "source_port_466",
      "source_port_467",
      "source_port_468",
      "source_port_469",
      "source_port_470",
      "source_port_471",
      "source_port_472",
      "source_port_473",
      "source_port_474",
      "source_port_475",
      "source_port_476",
      "source_port_477",
      "source_port_478",
      "source_port_479",
      "source_port_480",
      "source_port_481",
      "source_port_482",
      "source_port_483",
      "source_port_484",
      "source_port_485",
      "source_port_486",
      "source_port_487",
      "source_port_488",
      "source_port_489",
      "source_port_490",
      "source_port_491",
      "source_port_492",
      "source_port_493",
      "source_port_494",
      "source_port_495",
      "source_port_496",
      "source_port_497",
      "source_port_498",
      "source_port_499",
      "source_port_500",
      "source_port_501",
      "source_port_502",
      "source_port_503",
      "source_port_504",
      "source_port_505",
      "source_port_506",
      "source_port_507",
      "source_port_508",
      "source_port_509",
      "source_port_510",
      "source_port_511",
      "source_port_512",
      "source_port_513",
      "source_port_514",
      "source_port_515",
      "source_port_516",
      "source_port_517",
      "source_port_518",
      "source_port_519",
      "source_port_520",
      "source_port_521",
      "source_port_522",
      "source_port_523",
      "source_port_524",
      "source_port_525",
      "source_port_526",
      "source_port_527",
      "source_port_528",
      "source_port_529",
      "source_port_530",
      "source_port_531",
      "source_port_532",
      "source_port_533",
      "source_port_534",
      "source_port_535",
      "source_port_536",
      "source_port_537",
      "source_port_538",
      "source_port_539",
      "source_port_540",
      "source_port_541",
      "source_port_542",
      "source_port_543",
      "source_port_544",
      "source_port_545",
      "source_port_546",
      "source_port_547",
      "source_port_548",
      "source_port_549",
      "source_port_550",
      "source_port_551",
      "source_port_552",
      "source_port_553",
      "source_port_554",
      "source_port_555",
      "source_port_556",
      "source_port_557",
      "source_port_558",
      "source_port_559",
      "source_port_560",
      "source_port_561",
      "source_port_562",
      "source_port_563",
      "source_port_564",
      "source_port_565",
      "source_port_566",
      "source_port_567",
      "source_port_568",
      "source_port_569",
      "source_port_570",
      "source_port_571",
      "source_port_572"
    ],
    "subcircuit_id": "subcircuit_source_group_2"
  }
]